Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RST_USB_PHY0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RST_BUS_DMA		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RST_BUS_MMC0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RST_BUS_MMC1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RST_BUS_DRAM		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RST_BUS_SPI0		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RST_BUS_SPI1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RST_BUS_OTG		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RST_BUS_VE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RST_BUS_LCD		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RST_BUS_DEINTERLACE	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RST_BUS_CSI		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RST_BUS_TVD		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RST_BUS_TVE		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RST_BUS_DE_BE		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RST_BUS_DE_FE		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RST_BUS_CODEC		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RST_BUS_SPDIF		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RST_BUS_IR		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RST_BUS_RSB		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RST_BUS_I2S0		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RST_BUS_I2C0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RST_BUS_I2C1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RST_BUS_I2C2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RST_BUS_UART0		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RST_BUS_UART1		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RST_BUS_UART2		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */