^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is dual-licensed: you can use it either under the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * of the GPL or the X11 license, at your option. Note that this dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licensing only applies to this file, and not this project as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * whole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a) This file is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation; either version 2 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This file is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Or, alternatively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * b) Permission is hereby granted, free of charge, to any person
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * obtaining a copy of this software and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * files (the "Software"), to deal in the Software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * restriction, including without limitation the rights to use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Software is furnished to do so, subject to the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The above copyright notice and this permission notice shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * included in all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #ifndef _DT_BINDINGS_RST_SUN8I_R40_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define _DT_BINDINGS_RST_SUN8I_R40_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RST_USB_PHY0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RST_USB_PHY1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RST_USB_PHY2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RST_DRAM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RST_MBUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RST_BUS_MIPI_DSI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RST_BUS_CE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RST_BUS_DMA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RST_BUS_MMC0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RST_BUS_MMC1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RST_BUS_MMC2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RST_BUS_MMC3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RST_BUS_NAND 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RST_BUS_DRAM 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RST_BUS_EMAC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RST_BUS_TS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RST_BUS_HSTIMER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RST_BUS_SPI0 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RST_BUS_SPI1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RST_BUS_SPI2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RST_BUS_SPI3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RST_BUS_SATA 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RST_BUS_OTG 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RST_BUS_EHCI0 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RST_BUS_EHCI1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RST_BUS_EHCI2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RST_BUS_OHCI0 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RST_BUS_OHCI1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RST_BUS_OHCI2 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RST_BUS_VE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RST_BUS_MP 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RST_BUS_DEINTERLACE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RST_BUS_CSI0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RST_BUS_CSI1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RST_BUS_HDMI0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RST_BUS_HDMI1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RST_BUS_DE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RST_BUS_TVE0 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RST_BUS_TVE1 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RST_BUS_TVE_TOP 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RST_BUS_GMAC 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RST_BUS_GPU 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RST_BUS_TVD0 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RST_BUS_TVD1 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RST_BUS_TVD2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RST_BUS_TVD3 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RST_BUS_TVD_TOP 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RST_BUS_TCON_LCD0 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RST_BUS_TCON_LCD1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RST_BUS_TCON_TV0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RST_BUS_TCON_TV1 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RST_BUS_TCON_TOP 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RST_BUS_DBG 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RST_BUS_LVDS 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RST_BUS_CODEC 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RST_BUS_SPDIF 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RST_BUS_AC97 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RST_BUS_IR0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RST_BUS_IR1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RST_BUS_THS 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RST_BUS_KEYPAD 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RST_BUS_I2S0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RST_BUS_I2S1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RST_BUS_I2S2 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RST_BUS_I2C0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RST_BUS_I2C1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RST_BUS_I2C2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RST_BUS_I2C3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RST_BUS_CAN 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RST_BUS_SCR 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RST_BUS_PS20 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RST_BUS_PS21 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RST_BUS_I2C4 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RST_BUS_UART0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RST_BUS_UART1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RST_BUS_UART2 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RST_BUS_UART3 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RST_BUS_UART4 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RST_BUS_UART5 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RST_BUS_UART6 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RST_BUS_UART7 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags