Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: (GPL-2.0+ or MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_RESET_SUN50I_H6_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define RST_MBUS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RST_BUS_DE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RST_BUS_DEINTERLACE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RST_BUS_GPU		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RST_BUS_CE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RST_BUS_VE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RST_BUS_EMCE		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RST_BUS_VP9		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RST_BUS_DMA		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RST_BUS_MSGBOX		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RST_BUS_SPINLOCK	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RST_BUS_HSTIMER		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RST_BUS_DBG		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RST_BUS_PSI		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RST_BUS_PWM		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RST_BUS_IOMMU		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RST_BUS_DRAM		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RST_BUS_NAND		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RST_BUS_MMC0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RST_BUS_MMC1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RST_BUS_MMC2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RST_BUS_UART0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RST_BUS_UART1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RST_BUS_UART2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RST_BUS_UART3		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RST_BUS_I2C0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RST_BUS_I2C1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RST_BUS_I2C2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RST_BUS_I2C3		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RST_BUS_SCR0		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RST_BUS_SCR1		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RST_BUS_SPI0		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RST_BUS_SPI1		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RST_BUS_EMAC		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RST_BUS_TS		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RST_BUS_IR_TX		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RST_BUS_THS		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RST_BUS_I2S0		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RST_BUS_I2S1		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RST_BUS_I2S2		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RST_BUS_I2S3		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RST_BUS_SPDIF		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RST_BUS_DMIC		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RST_BUS_AUDIO_HUB	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RST_USB_PHY0		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RST_USB_PHY1		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RST_USB_PHY3		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RST_USB_HSIC		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RST_BUS_OHCI0		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RST_BUS_OHCI3		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RST_BUS_EHCI0		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RST_BUS_XHCI		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RST_BUS_EHCI3		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RST_BUS_OTG		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RST_BUS_PCIE		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RST_PCIE_POWERUP	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RST_BUS_HDMI		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RST_BUS_HDMI_SUB	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RST_BUS_TCON_TOP	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RST_BUS_TCON_LCD0	59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RST_BUS_TCON_TV0	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RST_BUS_CSI		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RST_BUS_HDCP		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */