^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_STM32MP1_RESET_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_STM32MP1_RESET_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define LTDC_R 3072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DSI_R 3076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DDRPERFM_R 3080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define USBPHY_R 3088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPI6_R 3136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define I2C4_R 3138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define I2C6_R 3139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define USART1_R 3140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STGEN_R 3156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GPIOZ_R 3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CRYP1_R 3204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HASH1_R 3205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RNG1_R 3206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AXIM_R 3216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GPU_R 3269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ETHMAC_R 3274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FMC_R 3276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QSPI_R 3278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SDMMC1_R 3280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SDMMC2_R 3281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRC1_R 3284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USBH_R 3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MDMA_R 3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCU_R 8225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TIM2_R 19456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TIM3_R 19457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TIM4_R 19458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TIM5_R 19459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TIM6_R 19460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TIM7_R 19461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TIM12_R 16462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TIM13_R 16463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TIM14_R 16464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPTIM1_R 19465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPI2_R 19467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPI3_R 19468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USART2_R 19470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USART3_R 19471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UART4_R 19472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define UART5_R 19473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define UART7_R 19474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define UART8_R 19475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C1_R 19477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define I2C2_R 19478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define I2C3_R 19479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2C5_R 19480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPDIF_R 19482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CEC_R 19483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DAC12_R 19485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MDIO_R 19847
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TIM1_R 19520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TIM8_R 19521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TIM15_R 19522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TIM16_R 19523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TIM17_R 19524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPI1_R 19528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPI4_R 19529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPI5_R 19530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USART6_R 19533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAI1_R 19536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAI2_R 19537
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAI3_R 19538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DFSDM_R 19540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FDCAN_R 19544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LPTIM2_R 19584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LPTIM3_R 19585
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LPTIM4_R 19586
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LPTIM5_R 19587
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SAI4_R 19592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SYSCFG_R 19595
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VREF_R 19597
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TMPSENS_R 19600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PMBCTRL_R 19601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DMA1_R 19648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DMA2_R 19649
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DMAMUX_R 19650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ADC12_R 19653
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define USBO_R 19656
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SDMMC3_R 19664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CAMITF_R 19712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CRYP2_R 19716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HASH2_R 19717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RNG2_R 19718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CRC2_R 19719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HSEM_R 19723
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MBOX_R 19724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPIOA_R 19776
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPIOB_R 19777
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPIOC_R 19778
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPIOD_R 19779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPIOE_R 19780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPIOF_R 19781
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPIOG_R 19782
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPIOH_R 19783
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPIOI_R 19784
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPIOJ_R 19785
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPIOK_R 19786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags