^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for the reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * based peripheral powerdown requests on the STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * STiH416 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_RESET_CONTROLLER_STIH416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define STIH416_EMISS_POWERDOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define STIH416_NAND_POWERDOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define STIH416_KEYSCAN_POWERDOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define STIH416_USB0_POWERDOWN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define STIH416_USB1_POWERDOWN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STIH416_USB2_POWERDOWN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define STIH416_USB3_POWERDOWN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STIH416_SATA0_POWERDOWN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STIH416_SATA1_POWERDOWN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STIH416_PCIE0_POWERDOWN 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STIH416_PCIE1_POWERDOWN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STIH416_ETH0_SOFTRESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STIH416_ETH1_SOFTRESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STIH416_IRB_SOFTRESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STIH416_USB0_SOFTRESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STIH416_USB1_SOFTRESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STIH416_USB2_SOFTRESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STIH416_USB3_SOFTRESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STIH416_SATA0_SOFTRESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STIH416_SATA1_SOFTRESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STIH416_PCIE0_SOFTRESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STIH416_PCIE1_SOFTRESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STIH416_AUD_DAC_SOFTRESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STIH416_HDTVOUT_SOFTRESET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STIH416_VTAC_M_RX_SOFTRESET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STIH416_VTAC_A_RX_SOFTRESET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STIH416_SYNC_HD_SOFTRESET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STIH416_SYNC_SD_SOFTRESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STIH416_BLITTER_SOFTRESET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STIH416_GPU_SOFTRESET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STIH416_VTAC_M_TX_SOFTRESET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STIH416_VTAC_A_TX_SOFTRESET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STIH416_VTG_AUX_SOFTRESET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STIH416_JPEG_DEC_SOFTRESET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STIH416_HVA_SOFTRESET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STIH416_COMPO_M_SOFTRESET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STIH416_COMPO_A_SOFTRESET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STIH416_VP8_DEC_SOFTRESET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STIH416_VTG_MAIN_SOFTRESET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STIH416_KEYSCAN_SOFTRESET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH416 */