Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants for the reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * based peripheral powerdown requests on the STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * STiH407 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_RESET_CONTROLLER_STIH407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Powerdown requests control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define STIH407_EMISS_POWERDOWN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define STIH407_NAND_POWERDOWN		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Synp GMAC PowerDown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define STIH407_ETH1_POWERDOWN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Powerdown requests control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define STIH407_USB3_POWERDOWN		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define STIH407_USB2_PORT1_POWERDOWN	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STIH407_USB2_PORT0_POWERDOWN	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define STIH407_PCIE1_POWERDOWN		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define STIH407_PCIE0_POWERDOWN		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STIH407_SATA1_POWERDOWN		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STIH407_SATA0_POWERDOWN		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Reset defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define STIH407_ETH1_SOFTRESET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STIH407_MMC1_SOFTRESET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define STIH407_PICOPHY_SOFTRESET	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define STIH407_IRB_SOFTRESET		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define STIH407_PCIE0_SOFTRESET		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define STIH407_PCIE1_SOFTRESET		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define STIH407_SATA0_SOFTRESET		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define STIH407_SATA1_SOFTRESET		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define STIH407_MIPHY0_SOFTRESET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define STIH407_MIPHY1_SOFTRESET	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define STIH407_MIPHY2_SOFTRESET	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define STIH407_SATA0_PWR_SOFTRESET	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define STIH407_SATA1_PWR_SOFTRESET	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define STIH407_DELTA_SOFTRESET		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define STIH407_BLITTER_SOFTRESET	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define STIH407_HDTVOUT_SOFTRESET	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STIH407_HDQVDP_SOFTRESET	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define STIH407_VDP_AUX_SOFTRESET	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STIH407_COMPO_SOFTRESET		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define STIH407_HDMI_TX_PHY_SOFTRESET	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define STIH407_JPEG_DEC_SOFTRESET	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STIH407_VP8_DEC_SOFTRESET	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define STIH407_GPU_SOFTRESET		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define STIH407_HVA_SOFTRESET		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define STIH407_ERAM_HVA_SOFTRESET	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define STIH407_LPM_SOFTRESET		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define STIH407_KEYSCAN_SOFTRESET	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define STIH407_USB2_PORT0_SOFTRESET	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define STIH407_USB2_PORT1_SOFTRESET	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define STIH407_ST231_AUD_SOFTRESET	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define STIH407_ST231_DMU_SOFTRESET	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define STIH407_ST231_GP0_SOFTRESET	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define STIH407_ST231_GP1_SOFTRESET	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Picophy reset defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define STIH407_PICOPHY0_RESET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define STIH407_PICOPHY1_RESET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define STIH407_PICOPHY2_RESET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */