^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * This header provides index for the HSDK reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define HSDK_APB_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define HSDK_AXI_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HSDK_ETH_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define HSDK_USB_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define HSDK_SDIO_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HSDK_HDMI_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HSDK_GFX_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HSDK_DMAC_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HSDK_EBI_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/