^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Realtek RTD1295 reset controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef DT_BINDINGS_RESET_RTD1295_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DT_BINDINGS_RESET_RTD1295_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* soft reset 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RTD1295_RSTN_MISC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTD1295_RSTN_NAT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RTD1295_RSTN_USB3_PHY0_POW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RTD1295_RSTN_GSPI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RTD1295_RSTN_USB3_P0_MDIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RTD1295_RSTN_SATA_0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTD1295_RSTN_USB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTD1295_RSTN_SATA_PHY_0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTD1295_RSTN_USB_PHY0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTD1295_RSTN_USB_PHY1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTD1295_RSTN_SATA_PHY_POW_0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTD1295_RSTN_SATA_FUNC_EXIST_0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RTD1295_RSTN_HDMI 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTD1295_RSTN_VE1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTD1295_RSTN_VE2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTD1295_RSTN_VE3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTD1295_RSTN_ETN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTD1295_RSTN_AIO 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTD1295_RSTN_GPU 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTD1295_RSTN_TVE 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTD1295_RSTN_VO 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTD1295_RSTN_LVDS 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTD1295_RSTN_SE 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTD1295_RSTN_DCU 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTD1295_RSTN_DC_PHY 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTD1295_RSTN_CP 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTD1295_RSTN_MD 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTD1295_RSTN_TP 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTD1295_RSTN_AE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTD1295_RSTN_NF 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTD1295_RSTN_MIPI 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTD1295_RSTN_RSA 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* soft reset 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTD1295_RSTN_ACPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTD1295_RSTN_JPEG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTD1295_RSTN_USB_PHY3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTD1295_RSTN_USB_PHY2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTD1295_RSTN_USB3_PHY1_POW 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RTD1295_RSTN_USB3_P1_MDIO 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RTD1295_RSTN_PCIE0_STITCH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RTD1295_RSTN_PCIE0_PHY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTD1295_RSTN_PCIE0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTD1295_RSTN_PCR_CNT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTD1295_RSTN_CR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RTD1295_RSTN_EMMC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RTD1295_RSTN_SDIO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RTD1295_RSTN_PCIE0_CORE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RTD1295_RSTN_PCIE0_POWER 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RTD1295_RSTN_PCIE0_NONSTICH 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RTD1295_RSTN_PCIE1_PHY 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RTD1295_RSTN_PCIE1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RTD1295_RSTN_I2C_5 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RTD1295_RSTN_PCIE1_STITCH 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RTD1295_RSTN_PCIE1_CORE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RTD1295_RSTN_PCIE1_POWER 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RTD1295_RSTN_PCIE1_NONSTICH 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RTD1295_RSTN_I2C_4 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RTD1295_RSTN_I2C_3 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RTD1295_RSTN_I2C_2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RTD1295_RSTN_I2C_1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RTD1295_RSTN_UR2 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RTD1295_RSTN_UR1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RTD1295_RSTN_MISC_SC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RTD1295_RSTN_CBUS_TX 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RTD1295_RSTN_SDS_PHY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* soft reset 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RTD1295_RSTN_SB2 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* soft reset 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RTD1295_RSTN_DCPHY_CRT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RTD1295_RSTN_DCPHY_ALERT_RX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RTD1295_RSTN_DCPHY_PTR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RTD1295_RSTN_DCPHY_LDO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RTD1295_RSTN_DCPHY_SSC_DIG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RTD1295_RSTN_HDMIRX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RTD1295_RSTN_CBUSRX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RTD1295_RSTN_SATA_PHY_POW_1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RTD1295_RSTN_SATA_FUNC_EXIST_1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RTD1295_RSTN_SATA_PHY_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RTD1295_RSTN_SATA_1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RTD1295_RSTN_FAN 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RTD1295_RSTN_HDMIRX_WRAP 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RTD1295_RSTN_PCIE0_PHY_MDIO 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RTD1295_RSTN_PCIE1_PHY_MDIO 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RTD1295_RSTN_DISP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* iso reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RTD1295_ISO_RSTN_IR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RTD1295_ISO_RSTN_CEC0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RTD1295_ISO_RSTN_CEC1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RTD1295_ISO_RSTN_DP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RTD1295_ISO_RSTN_CBUSTX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RTD1295_ISO_RSTN_CBUSRX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RTD1295_ISO_RSTN_EFUSE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RTD1295_ISO_RSTN_UR0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RTD1295_ISO_RSTN_GMAC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RTD1295_ISO_RSTN_GPHY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RTD1295_ISO_RSTN_I2C_0 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RTD1295_ISO_RSTN_I2C_1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RTD1295_ISO_RSTN_CBUS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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