Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Realtek RTD1195 reset controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2017 Andreas Färber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef DT_BINDINGS_RESET_RTD1195_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define DT_BINDINGS_RESET_RTD1195_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* soft reset 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RTD1195_RSTN_MISC		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTD1195_RSTN_RNG		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RTD1195_RSTN_USB3_POW		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RTD1195_RSTN_GSPI		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RTD1195_RSTN_USB3_P0_MDIO	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RTD1195_RSTN_VE_H265		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTD1195_RSTN_USB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTD1195_RSTN_USB_PHY0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTD1195_RSTN_USB_PHY1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTD1195_RSTN_HDMIRX		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTD1195_RSTN_HDMI		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTD1195_RSTN_ETN		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RTD1195_RSTN_AIO		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTD1195_RSTN_GPU		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTD1195_RSTN_VE_H264		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTD1195_RSTN_VE_JPEG		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTD1195_RSTN_TVE		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTD1195_RSTN_VO			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTD1195_RSTN_LVDS		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTD1195_RSTN_SE			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTD1195_RSTN_DCU		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTD1195_RSTN_DC_PHY		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTD1195_RSTN_CP			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTD1195_RSTN_MD			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTD1195_RSTN_TP			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTD1195_RSTN_AE			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTD1195_RSTN_NF			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTD1195_RSTN_MIPI		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* soft reset 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTD1195_RSTN_ACPU		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTD1195_RSTN_VCPU		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTD1195_RSTN_PCR		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RTD1195_RSTN_CR			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTD1195_RSTN_EMMC		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTD1195_RSTN_SDIO		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTD1195_RSTN_I2C_5		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTD1195_RSTN_RTC		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTD1195_RSTN_I2C_4		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RTD1195_RSTN_I2C_3		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RTD1195_RSTN_I2C_2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RTD1195_RSTN_I2C_1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTD1195_RSTN_UR1		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* soft reset 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RTD1195_RSTN_SB2		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* iso soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RTD1195_ISO_RSTN_VFD		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RTD1195_ISO_RSTN_IR		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RTD1195_ISO_RSTN_CEC0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RTD1195_ISO_RSTN_CEC1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RTD1195_ISO_RSTN_DP		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RTD1195_ISO_RSTN_CBUSTX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RTD1195_ISO_RSTN_CBUSRX		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RTD1195_ISO_RSTN_EFUSE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RTD1195_ISO_RSTN_UR0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RTD1195_ISO_RSTN_GMAC		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RTD1195_ISO_RSTN_GPHY		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RTD1195_ISO_RSTN_I2C_0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RTD1195_ISO_RSTN_I2C_6		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RTD1195_ISO_RSTN_CBUS		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif