Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_RESET_MSM_MMCC_8974_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define SPDM_RESET			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SPDM_RM_RESET			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define VENUS0_RESET			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MDSS_RESET			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CAMSS_PHY0_RESET		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CAMSS_PHY1_RESET		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CAMSS_PHY2_RESET		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CAMSS_CSI0_RESET		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CAMSS_CSI0PHY_RESET		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CAMSS_CSI0RDI_RESET		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CAMSS_CSI0PIX_RESET		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CAMSS_CSI1_RESET		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CAMSS_CSI1PHY_RESET		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CAMSS_CSI1RDI_RESET		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CAMSS_CSI1PIX_RESET		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CAMSS_CSI2_RESET		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CAMSS_CSI2PHY_RESET		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CAMSS_CSI2RDI_RESET		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CAMSS_CSI2PIX_RESET		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CAMSS_CSI3_RESET		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CAMSS_CSI3PHY_RESET		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CAMSS_CSI3RDI_RESET		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CAMSS_CSI3PIX_RESET		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CAMSS_ISPIF_RESET		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CAMSS_CCI_RESET			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CAMSS_MCLK0_RESET		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CAMSS_MCLK1_RESET		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CAMSS_MCLK2_RESET		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CAMSS_MCLK3_RESET		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CAMSS_GP0_RESET			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CAMSS_GP1_RESET			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CAMSS_TOP_RESET			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CAMSS_MICRO_RESET		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CAMSS_JPEG_RESET		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CAMSS_VFE_RESET			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CAMSS_CSI_VFE0_RESET		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CAMSS_CSI_VFE1_RESET		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OXILI_RESET			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OXILICX_RESET			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OCMEMCX_RESET			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMSS_RBCRP_RESET		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMSSNOCAHB_RESET		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMSSNOCAXI_RESET		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OCMEMNOC_RESET			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif