^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_RESET_MSM_MMCC_8960_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define VPE_AXI_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IJPEG_AXI_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MPD_AXI_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VFE_AXI_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SP_AXI_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define VCODEC_AXI_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ROT_AXI_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VCODEC_AXI_A_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define VCODEC_AXI_B_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FAB_S3_AXI_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FAB_S2_AXI_RESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FAB_S1_AXI_RESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FAB_S0_AXI_RESET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SMMU_GFX3D_ABH_RESET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SMMU_VPE_AHB_RESET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMMU_VFE_AHB_RESET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SMMU_ROT_AHB_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SMMU_VCODEC_B_AHB_RESET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SMMU_VCODEC_A_AHB_RESET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMMU_MDP1_AHB_RESET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMMU_MDP0_AHB_RESET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMMU_JPEGD_AHB_RESET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMMU_IJPEG_AHB_RESET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMMU_GFX2D0_AHB_RESET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SMMU_GFX2D1_AHB_RESET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APU_AHB_RESET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CSI_AHB_RESET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TV_ENC_AHB_RESET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VPE_AHB_RESET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FABRIC_AHB_RESET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GFX2D0_AHB_RESET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GFX2D1_AHB_RESET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GFX3D_AHB_RESET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HDMI_AHB_RESET 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MSSS_IMEM_AHB_RESET 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IJPEG_AHB_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DSI_M_AHB_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DSI_S_AHB_RESET 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JPEGD_AHB_RESET 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MDP_AHB_RESET 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ROT_AHB_RESET 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VCODEC_AHB_RESET 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VFE_AHB_RESET 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DSI2_M_AHB_RESET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DSI2_S_AHB_RESET 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CSIPHY2_RESET 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CSI_PIX1_RESET 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSIPHY0_RESET 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CSIPHY1_RESET 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DSI2_RESET 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VFE_CSI_RESET 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MDP_RESET 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AMP_RESET 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define JPEGD_RESET 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSI1_RESET 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define VPE_RESET 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMSS_FABRIC_RESET 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VFE_RESET 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GFX2D0_RESET 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GFX2D1_RESET 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GFX3D_RESET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HDMI_RESET 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMSS_IMEM_RESET 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IJPEG_RESET 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CSI0_RESET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DSI_RESET 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VCODEC_RESET 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MDP_TV_RESET 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MDP_VSYNC_RESET 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ROT_RESET 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TV_HDMI_RESET 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TV_ENC_RESET 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CSI2_RESET 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CSI_RDI1_RESET 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CSI_RDI2_RESET 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GFX3D_AXI_RESET 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VCAP_AXI_RESET 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SMMU_VCAP_AHB_RESET 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VCAP_AHB_RESET 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CSI_RDI_RESET 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CSI_PIX_RESET 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VCAP_NPL_RESET 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VCAP_RESET 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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