^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_RESET_MSM_GCC_8916_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GCC_BLSP1_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GCC_BLSP1_QUP1_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define GCC_BLSP1_UART1_BCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GCC_BLSP1_QUP2_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GCC_BLSP1_UART2_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GCC_BLSP1_QUP3_BCR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GCC_BLSP1_QUP4_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GCC_BLSP1_QUP5_BCR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GCC_BLSP1_QUP6_BCR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GCC_IMEM_BCR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GCC_SMMU_BCR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GCC_APSS_TCU_BCR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GCC_SMMU_XPU_BCR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GCC_PCNOC_TBU_BCR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GCC_PRNG_BCR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GCC_BOOT_ROM_BCR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GCC_CRYPTO_BCR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GCC_SEC_CTRL_BCR 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GCC_AUDIO_CORE_BCR 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GCC_ULT_AUDIO_BCR 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GCC_DEHR_BCR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GCC_SYSTEM_NOC_BCR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GCC_PCNOC_BCR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GCC_TCSR_BCR 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GCC_QDSS_BCR 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GCC_DCD_BCR 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GCC_MSG_RAM_BCR 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GCC_MPM_BCR 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GCC_SPMI_BCR 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GCC_SPDM_BCR 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GCC_MM_SPDM_BCR 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GCC_BIMC_BCR 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GCC_RBCPR_BCR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GCC_TLMM_BCR 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GCC_USB_HS_BCR 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GCC_USB2A_PHY_BCR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GCC_SDCC1_BCR 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GCC_SDCC2_BCR 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GCC_PDM_BCR 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GCC_SNOC_BUS_TIMEOUT0_BCR 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GCC_PCNOC_BUS_TIMEOUT0_BCR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCC_PCNOC_BUS_TIMEOUT1_BCR 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCC_PCNOC_BUS_TIMEOUT2_BCR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GCC_PCNOC_BUS_TIMEOUT3_BCR 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GCC_PCNOC_BUS_TIMEOUT4_BCR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GCC_PCNOC_BUS_TIMEOUT5_BCR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GCC_PCNOC_BUS_TIMEOUT6_BCR 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GCC_PCNOC_BUS_TIMEOUT7_BCR 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GCC_PCNOC_BUS_TIMEOUT8_BCR 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GCC_PCNOC_BUS_TIMEOUT9_BCR 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GCC_MMSS_BCR 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GCC_VENUS0_BCR 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GCC_MDSS_BCR 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GCC_CAMSS_PHY0_BCR 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GCC_CAMSS_CSI0_BCR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCC_CAMSS_CSI0PHY_BCR 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GCC_CAMSS_CSI0RDI_BCR 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GCC_CAMSS_CSI0PIX_BCR 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GCC_CAMSS_PHY1_BCR 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_CAMSS_CSI1_BCR 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_CAMSS_CSI1PHY_BCR 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_CAMSS_CSI1RDI_BCR 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_CAMSS_CSI1PIX_BCR 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_CAMSS_ISPIF_BCR 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_CAMSS_CCI_BCR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_CAMSS_MCLK0_BCR 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_CAMSS_MCLK1_BCR 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_CAMSS_GP0_BCR 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_CAMSS_GP1_BCR 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_CAMSS_TOP_BCR 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_CAMSS_MICRO_BCR 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_CAMSS_JPEG_BCR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_CAMSS_VFE_BCR 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_CAMSS_CSI_VFE0_BCR 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_OXILI_BCR 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_GMEM_BCR 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_CAMSS_AHB_BCR 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_MDP_TBU_BCR 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_GFX_TBU_BCR 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_GFX_TCU_BCR 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_MSS_TBU_AXI_BCR 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_MSS_TBU_GSS_AXI_BCR 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_MSS_TBU_Q6_AXI_BCR 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_GTCU_AHB_BCR 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_SMMU_CFG_BCR 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_VFE_TBU_BCR 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GCC_VENUS_TBU_BCR 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GCC_JPEG_TBU_BCR 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GCC_PRONTO_TBU_BCR 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GCC_SMMU_CATS_BCR 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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