^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_RESET_MSM_GCC_8660_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define AFAB_CORE_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SCSS_SYS_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SCSS_SYS_POR_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AFAB_SMPSS_S_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AFAB_SMPSS_M1_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AFAB_SMPSS_M0_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AFAB_EBI1_S_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SFAB_CORE_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SFAB_ADM0_M0_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SFAB_ADM0_M1_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SFAB_ADM0_M2_RESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADM0_C2_RESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADM0_C1_RESET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADM0_C0_RESET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADM0_PBUS_RESET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADM0_RESET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SFAB_ADM1_M0_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SFAB_ADM1_M1_RESET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SFAB_ADM1_M2_RESET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MMFAB_ADM1_M3_RESET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ADM1_C3_RESET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ADM1_C2_RESET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADM1_C1_RESET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ADM1_C0_RESET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ADM1_PBUS_RESET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ADM1_RESET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMEM0_RESET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SFAB_LPASS_Q6_RESET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SFAB_AFAB_M_RESET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AFAB_SFAB_M0_RESET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFAB_SFAB_M1_RESET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DFAB_CORE_RESET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SFAB_DFAB_M_RESET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DFAB_SFAB_M_RESET 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DFAB_SWAY0_RESET 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DFAB_SWAY1_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DFAB_ARB0_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DFAB_ARB1_RESET 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PPSS_PROC_RESET 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PPSS_RESET 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PMEM_RESET 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMA_BAM_RESET 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SIC_RESET 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPS_TIC_RESET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CFBP0_RESET 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CFBP1_RESET 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CFBP2_RESET 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EBI2_RESET 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SFAB_CFPB_M_RESET 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CFPB_MASTER_RESET 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SFAB_CFPB_S_RESET 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CFPB_SPLITTER_RESET 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TSIF_RESET 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CE1_RESET 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CE2_RESET 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SFAB_SFPB_M_RESET 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SFAB_SFPB_S_RESET 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RPM_PROC_RESET 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RPM_BUS_RESET 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RPM_MSG_RAM_RESET 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PMIC_ARB0_RESET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMIC_ARB1_RESET 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PMIC_SSBI2_RESET 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDC1_RESET 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDC2_RESET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDC3_RESET 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDC4_RESET 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SDC5_RESET 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB_HS1_RESET 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USB_HS2_XCVR_RESET 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define USB_HS2_RESET 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define USB_FS1_XCVR_RESET 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define USB_FS1_RESET 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define USB_FS2_XCVR_RESET 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define USB_FS2_RESET 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GSBI1_RESET 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GSBI2_RESET 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GSBI3_RESET 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GSBI4_RESET 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GSBI5_RESET 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GSBI6_RESET 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GSBI7_RESET 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GSBI8_RESET 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GSBI9_RESET 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GSBI10_RESET 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GSBI11_RESET 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GSBI12_RESET 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPDM_RESET 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SEC_CTRL_RESET 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TLMM_H_RESET 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TLMM_RESET 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MARRM_PWRON_RESET 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MARM_RESET 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAHB1_RESET 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SFAB_MSS_S_RESET 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAHB2_RESET 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MODEM_SW_AHB_RESET 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MODEM_RESET 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SFAB_MSS_MDM1_RESET 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SFAB_MSS_MDM0_RESET 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSS_SLP_RESET 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSS_MARM_SAW_RESET 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSS_WDOG_RESET 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TSSC_RESET 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PDM_RESET 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCSS_CORE0_RESET 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SCSS_CORE0_POR_RESET 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SCSS_CORE1_RESET 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCSS_CORE1_POR_RESET 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MPM_RESET 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EBI1_1X_DIV_RESET 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EBI1_RESET 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SFAB_SMPSS_S_RESET 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USB_PHY0_RESET 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define USB_PHY1_RESET 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PRNG_RESET 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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