^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author : Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DT_BINDINGS_RESET_GCC_MDM9615_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SFAB_MSS_Q6_SW_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SFAB_MSS_Q6_FW_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define QDSS_STM_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AFAB_SMPSS_S_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AFAB_SMPSS_M1_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AFAB_SMPSS_M0_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AFAB_EBI1_CH0_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AFAB_EBI1_CH1_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SFAB_ADM0_M0_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SFAB_ADM0_M1_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SFAB_ADM0_M2_RESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADM0_C2_RESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ADM0_C1_RESET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ADM0_C0_RESET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ADM0_PBUS_RESET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ADM0_RESET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QDSS_CLKS_SW_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QDSS_POR_RESET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QDSS_TSCTR_RESET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QDSS_HRESET_RESET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QDSS_AXI_RESET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QDSS_DBG_RESET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_A_RESET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_AUX_RESET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_H_RESET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SFAB_PCIE_M_RESET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SFAB_PCIE_S_RESET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SFAB_MSS_M_RESET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SFAB_USB3_M_RESET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SFAB_RIVA_M_RESET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SFAB_LPASS_RESET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SFAB_AFAB_M_RESET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AFAB_SFAB_M0_RESET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AFAB_SFAB_M1_RESET 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SFAB_SATA_S_RESET 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SFAB_DFAB_M_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DFAB_SFAB_M_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DFAB_SWAY0_RESET 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DFAB_SWAY1_RESET 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DFAB_ARB0_RESET 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DFAB_ARB1_RESET 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PPSS_PROC_RESET 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PPSS_RESET 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DMA_BAM_RESET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPS_TIC_H_RESET 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLIMBUS_H_RESET 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SFAB_CFPB_M_RESET 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SFAB_CFPB_S_RESET 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TSIF_H_RESET 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CE1_H_RESET 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CE1_CORE_RESET 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CE1_SLEEP_RESET 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CE2_H_RESET 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CE2_CORE_RESET 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SFAB_SFPB_M_RESET 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SFAB_SFPB_S_RESET 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RPM_PROC_RESET 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PMIC_SSBI2_RESET 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDC1_RESET 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDC2_RESET 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDC3_RESET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDC4_RESET 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDC5_RESET 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DFAB_A2_RESET 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USB_HS1_RESET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USB_HSIC_RESET 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define USB_FS1_XCVR_RESET 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define USB_FS1_RESET 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define USB_FS2_XCVR_RESET 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define USB_FS2_RESET 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GSBI1_RESET 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GSBI2_RESET 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GSBI3_RESET 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GSBI4_RESET 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GSBI5_RESET 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GSBI6_RESET 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GSBI7_RESET 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GSBI8_RESET 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GSBI9_RESET 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GSBI10_RESET 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GSBI11_RESET 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GSBI12_RESET 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPDM_RESET 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TLMM_H_RESET 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SFAB_MSS_S_RESET 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MSS_SLP_RESET 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MSS_Q6SW_JTAG_RESET 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MSS_Q6FW_JTAG_RESET 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MSS_RESET 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SATA_H_RESET 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SATA_RXOOB_RESE 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SATA_PMALIVE_RESET 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SATA_SFAB_M_RESET 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TSSC_RESET 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PDM_RESET 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MPM_H_RESET 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MPM_RESET 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SFAB_SMPSS_S_RESET 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PRNG_RESET 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RIVA_RESET 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define USB_HS3_RESET 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USB_HS4_RESET 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CE3_RESET 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIE_EXT_PCI_RESET 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIE_PHY_RESET 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCIE_PCI_RESET 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCIE_POR_RESET 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCIE_HCLK_RESET 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCIE_ACLK_RESET 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CE3_H_RESET 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SFAB_CE3_M_RESET 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SFAB_CE3_S_RESET 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SATA_RESET 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CE3_SLEEP_RESET 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GSS_SLP_RESET 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GSS_RESET 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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