^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_RESET_IPQ_806X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_RESET_IPQ_806X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define QDSS_STM_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AFAB_SMPSS_S_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AFAB_SMPSS_M1_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AFAB_SMPSS_M0_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AFAB_EBI1_CH0_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AFAB_EBI1_CH1_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SFAB_ADM0_M0_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SFAB_ADM0_M1_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SFAB_ADM0_M2_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ADM0_C2_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ADM0_C1_RESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ADM0_C0_RESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ADM0_PBUS_RESET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ADM0_RESET 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QDSS_CLKS_SW_RESET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QDSS_POR_RESET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QDSS_TSCTR_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QDSS_HRESET_RESET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QDSS_AXI_RESET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QDSS_DBG_RESET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SFAB_PCIE_M_RESET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SFAB_PCIE_S_RESET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIE_EXT_RESET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIE_PHY_RESET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_PCI_RESET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_POR_RESET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_HCLK_RESET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_ACLK_RESET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SFAB_LPASS_RESET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SFAB_AFAB_M_RESET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AFAB_SFAB_M0_RESET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AFAB_SFAB_M1_RESET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SFAB_SATA_S_RESET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SFAB_DFAB_M_RESET 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DFAB_SFAB_M_RESET 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DFAB_SWAY0_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DFAB_SWAY1_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DFAB_ARB0_RESET 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DFAB_ARB1_RESET 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PPSS_PROC_RESET 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PPSS_RESET 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMA_BAM_RESET 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPS_TIC_H_RESET 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SFAB_CFPB_M_RESET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SFAB_CFPB_S_RESET 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TSIF_H_RESET 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CE1_H_RESET 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CE1_CORE_RESET 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CE1_SLEEP_RESET 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CE2_H_RESET 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CE2_CORE_RESET 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SFAB_SFPB_M_RESET 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SFAB_SFPB_S_RESET 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RPM_PROC_RESET 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PMIC_SSBI2_RESET 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDC1_RESET 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDC2_RESET 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDC3_RESET 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDC4_RESET 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define USB_HS1_RESET 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define USB_HSIC_RESET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define USB_FS1_XCVR_RESET 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define USB_FS1_RESET 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GSBI1_RESET 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GSBI2_RESET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GSBI3_RESET 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GSBI4_RESET 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GSBI5_RESET 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GSBI6_RESET 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GSBI7_RESET 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SPDM_RESET 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SEC_CTRL_RESET 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TLMM_H_RESET 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SFAB_SATA_M_RESET 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SATA_RESET 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TSSC_RESET 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PDM_RESET 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MPM_H_RESET 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MPM_RESET 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SFAB_SMPSS_S_RESET 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PRNG_RESET 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SFAB_CE3_M_RESET 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SFAB_CE3_S_RESET 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CE3_SLEEP_RESET 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCIE_1_M_RESET 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCIE_1_S_RESET 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCIE_1_EXT_RESET 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCIE_1_PHY_RESET 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCIE_1_PCI_RESET 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCIE_1_POR_RESET 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCIE_1_HCLK_RESET 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCIE_1_ACLK_RESET 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCIE_2_M_RESET 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCIE_2_S_RESET 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCIE_2_EXT_RESET 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCIE_2_PHY_RESET 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCIE_2_PCI_RESET 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCIE_2_POR_RESET 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIE_2_HCLK_RESET 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCIE_2_ACLK_RESET 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SFAB_USB30_S_RESET 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SFAB_USB30_M_RESET 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define USB30_0_PORT2_HS_PHY_RESET 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define USB30_0_MASTER_RESET 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define USB30_0_SLEEP_RESET 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define USB30_0_UTMI_PHY_RESET 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define USB30_0_POWERON_RESET 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define USB30_0_PHY_RESET 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define USB30_1_MASTER_RESET 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define USB30_1_SLEEP_RESET 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define USB30_1_UTMI_PHY_RESET 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define USB30_1_POWERON_RESET 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USB30_1_PHY_RESET 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define NSSFB0_RESET 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define NSSFB1_RESET 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define UBI32_CORE1_CLKRST_CLAMP_RESET 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define UBI32_CORE1_CLAMP_RESET 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UBI32_CORE1_AHB_RESET 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define UBI32_CORE1_AXI_RESET 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define UBI32_CORE2_CLKRST_CLAMP_RESET 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define UBI32_CORE2_CLAMP_RESET 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define UBI32_CORE2_AHB_RESET 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define UBI32_CORE2_AXI_RESET 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GMAC_CORE1_RESET 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GMAC_CORE2_RESET 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GMAC_CORE3_RESET 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GMAC_CORE4_RESET 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GMAC_AHB_RESET 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define NSS_CH0_RST_RX_CLK_N_RESET 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define NSS_CH0_RST_TX_CLK_N_RESET 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define NSS_CH0_RST_RX_125M_N_RESET 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define NSS_CH0_HW_RST_RX_125M_N_RESET 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NSS_CH0_RST_TX_125M_N_RESET 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define NSS_CH1_RST_RX_CLK_N_RESET 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define NSS_CH1_RST_TX_CLK_N_RESET 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define NSS_CH1_RST_RX_125M_N_RESET 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define NSS_CH1_HW_RST_RX_125M_N_RESET 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define NSS_CH1_RST_TX_125M_N_RESET 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define NSS_CH2_RST_RX_CLK_N_RESET 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define NSS_CH2_RST_TX_CLK_N_RESET 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define NSS_CH2_RST_RX_125M_N_RESET 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define NSS_CH2_HW_RST_RX_125M_N_RESET 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define NSS_CH2_RST_TX_125M_N_RESET 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define NSS_CH3_RST_RX_CLK_N_RESET 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define NSS_CH3_RST_TX_CLK_N_RESET 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define NSS_CH3_RST_RX_125M_N_RESET 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define NSS_CH3_HW_RST_RX_125M_N_RESET 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define NSS_CH3_RST_TX_125M_N_RESET 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define NSS_RST_RX_250M_125M_N_RESET 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define NSS_RST_TX_250M_125M_N_RESET 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define NSS_QSGMII_TXPI_RST_N_RESET 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NSS_QSGMII_CDR_RST_N_RESET 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NSS_SGMII2_CDR_RST_N_RESET 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NSS_SGMII3_CDR_RST_N_RESET 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define NSS_CAL_PRBS_RST_N_RESET 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define NSS_LCKDT_RST_N_RESET 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define NSS_SRDS_N_RESET 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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