^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_RESET_IPQ_GCC_6018_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GCC_BLSP1_BCR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GCC_BLSP1_QUP1_BCR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define GCC_BLSP1_UART1_BCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GCC_BLSP1_QUP2_BCR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GCC_BLSP1_UART2_BCR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GCC_BLSP1_QUP3_BCR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GCC_BLSP1_UART3_BCR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GCC_BLSP1_QUP4_BCR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GCC_BLSP1_UART4_BCR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GCC_BLSP1_QUP5_BCR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GCC_BLSP1_UART5_BCR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GCC_BLSP1_QUP6_BCR 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GCC_BLSP1_UART6_BCR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GCC_IMEM_BCR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GCC_SMMU_BCR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GCC_APSS_TCU_BCR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GCC_SMMU_XPU_BCR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GCC_PCNOC_TBU_BCR 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GCC_SMMU_CFG_BCR 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GCC_PRNG_BCR 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GCC_BOOT_ROM_BCR 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GCC_CRYPTO_BCR 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GCC_WCSS_BCR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GCC_WCSS_Q6_BCR 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GCC_NSS_BCR 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GCC_SEC_CTRL_BCR 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GCC_DDRSS_BCR 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GCC_SYSTEM_NOC_BCR 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GCC_PCNOC_BCR 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GCC_TCSR_BCR 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GCC_QDSS_BCR 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GCC_DCD_BCR 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GCC_MSG_RAM_BCR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GCC_MPM_BCR 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GCC_SPDM_BCR 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GCC_RBCPR_BCR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GCC_RBCPR_MX_BCR 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GCC_TLMM_BCR 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GCC_RBCPR_WCSS_BCR 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GCC_USB0_PHY_BCR 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GCC_USB3PHY_0_PHY_BCR 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCC_USB0_BCR 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCC_USB1_BCR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GCC_QUSB2_0_PHY_BCR 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GCC_QUSB2_1_PHY_BCR 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GCC_SDCC1_BCR 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GCC_SNOC_BUS_TIMEOUT0_BCR 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GCC_SNOC_BUS_TIMEOUT1_BCR 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GCC_SNOC_BUS_TIMEOUT2_BCR 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GCC_PCNOC_BUS_TIMEOUT0_BCR 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GCC_PCNOC_BUS_TIMEOUT1_BCR 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GCC_PCNOC_BUS_TIMEOUT2_BCR 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GCC_PCNOC_BUS_TIMEOUT3_BCR 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GCC_PCNOC_BUS_TIMEOUT4_BCR 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GCC_PCNOC_BUS_TIMEOUT5_BCR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GCC_PCNOC_BUS_TIMEOUT6_BCR 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GCC_PCNOC_BUS_TIMEOUT7_BCR 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GCC_PCNOC_BUS_TIMEOUT8_BCR 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GCC_PCNOC_BUS_TIMEOUT9_BCR 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GCC_UNIPHY0_BCR 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GCC_UNIPHY1_BCR 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GCC_CMN_12GPLL_BCR 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GCC_QPIC_BCR 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GCC_MDIO_BCR 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GCC_WCSS_CORE_TBU_BCR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GCC_WCSS_Q6_TBU_BCR 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GCC_USB0_TBU_BCR 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GCC_PCIE0_TBU_BCR 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GCC_PCIE0_BCR 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GCC_PCIE0_PHY_BCR 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GCC_PCIE0PHY_PHY_BCR 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GCC_PCIE0_LINK_DOWN_BCR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GCC_DCC_BCR 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GCC_SMMU_CATS_BCR 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GCC_UBI0_AXI_ARES 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GCC_UBI0_AHB_ARES 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GCC_UBI0_NC_AXI_ARES 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GCC_UBI0_DBG_ARES 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GCC_UBI0_CORE_CLAMP_ENABLE 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GCC_UBI0_CLKRST_CLAMP_ENABLE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GCC_UBI0_UTCM_ARES 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GCC_NSS_CFG_ARES 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GCC_NSS_NOC_ARES 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GCC_NSS_CRYPTO_ARES 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GCC_NSS_CSR_ARES 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GCC_NSS_CE_APB_ARES 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GCC_NSS_CE_AXI_ARES 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GCC_NSSNOC_CE_APB_ARES 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GCC_NSSNOC_CE_AXI_ARES 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GCC_NSSNOC_UBI0_AHB_ARES 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GCC_NSSNOC_SNOC_ARES 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GCC_NSSNOC_CRYPTO_ARES 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GCC_NSSNOC_ATB_ARES 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GCC_NSSNOC_QOSGEN_REF_ARES 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GCC_NSSNOC_TIMEOUT_REF_ARES 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GCC_PCIE0_PIPE_ARES 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCC_PCIE0_SLEEP_ARES 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GCC_PCIE0_CORE_STICKY_ARES 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GCC_PCIE0_AXI_MASTER_ARES 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCC_PCIE0_AXI_SLAVE_ARES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCC_PCIE0_AHB_ARES 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GCC_PPE_FULL_RESET 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GCC_UNIPHY0_SOFT_RESET 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GCC_UNIPHY0_XPCS_RESET 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GCC_UNIPHY1_SOFT_RESET 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GCC_UNIPHY1_XPCS_RESET 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GCC_EDMA_HW_RESET 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GCC_ADSS_BCR 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GCC_NSS_NOC_TBU_BCR 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GCC_NSSPORT1_RESET 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GCC_NSSPORT2_RESET 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GCC_NSSPORT3_RESET 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GCC_NSSPORT4_RESET 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GCC_NSSPORT5_RESET 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GCC_UNIPHY0_PORT1_ARES 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GCC_UNIPHY0_PORT2_ARES 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GCC_UNIPHY0_PORT3_ARES 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GCC_UNIPHY0_PORT4_ARES 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GCC_UNIPHY0_PORT5_ARES 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GCC_UNIPHY0_PORT_4_5_RESET 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GCC_UNIPHY0_PORT_4_RESET 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GCC_LPASS_BCR 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GCC_UBI32_TBU_BCR 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GCC_LPASS_TBU_BCR 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GCC_WCSSAON_RESET 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GCC_LPASS_Q6_AXIM_ARES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GCC_LPASS_Q6SS_TRIG_ARES 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GCC_LPASS_Q6_ATBM_AT_ARES 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GCC_LPASS_Q6_PCLKDBG_ARES 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GCC_LPASS_CORE_AXIM_ARES 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GCC_LPASS_SNOC_CFG_ARES 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GCC_WCSS_DBG_ARES 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GCC_WCSS_ECAHB_ARES 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GCC_WCSS_ACMT_ARES 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GCC_WCSS_DBG_BDG_ARES 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GCC_WCSS_AHB_S_ARES 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GCC_WCSS_AXI_M_ARES 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GCC_Q6SS_DBG_ARES 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GCC_Q6_AHB_S_ARES 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GCC_Q6_AHB_ARES 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GCC_Q6_AXIM2_ARES 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GCC_Q6_AXIM_ARES 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GCC_UBI0_CORE_ARES 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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