^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef DT_RESET_OXSEMI_OX820_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define DT_RESET_OXSEMI_OX820_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RESET_SCU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RESET_LEON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RESET_ARM0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RESET_ARM1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_USBHS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_USBPHYA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_MAC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_PCIEA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_SGDMA 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_CIPHER 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_DDR 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_SATA 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_SATA_LINK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_SATA_PHY 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESET_PCIEPHY 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RESET_NAND 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_GPIO 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_UART1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_UART2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_MISC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_I2S 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_SD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_MAC_2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_PCIEB 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_VIDEO 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_DDR_PHY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_USBPHYB 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_USBDEV 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Reserved 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_ARMDBG 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RESET_PLLA 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_PLLB 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif /* DT_RESET_OXSEMI_OX820_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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