Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef DT_RESET_OXSEMI_OX810SE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define DT_RESET_OXSEMI_OX810SE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define RESET_ARM	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RESET_COPRO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Reserved		2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Reserved		3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_USBHS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_USBHSPHY	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_MAC	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_PCI	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_DMA	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_DPE	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_DDR	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_SATA	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_SATA_LINK	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_SATA_PHY	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  /* Reserved		14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RESET_NAND	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_GPIO	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_UART1	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_UART2	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_MISC	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_I2S	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_AHB_MON	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_UART3	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_UART4	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_SGDMA	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Reserved		25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Reserved		26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Reserved		27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Reserved		28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Reserved		29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Reserved		30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_BUS	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif /* DT_RESET_OXSEMI_OX810SE_H */