^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2019 Nuvoton Technology corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef _DT_BINDINGS_NPCM7XX_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define _DT_BINDINGS_NPCM7XX_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define NPCM7XX_RESET_IPSRST1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define NPCM7XX_RESET_IPSRST2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define NPCM7XX_RESET_IPSRST3 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define NPCM7XX_RESET_FIU3 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NPCM7XX_RESET_UDC1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NPCM7XX_RESET_EMC1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NPCM7XX_RESET_UART_2_3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NPCM7XX_RESET_UDC2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NPCM7XX_RESET_PECI 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NPCM7XX_RESET_AES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NPCM7XX_RESET_UART_0_1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NPCM7XX_RESET_MC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NPCM7XX_RESET_SMB2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NPCM7XX_RESET_SMB3 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define NPCM7XX_RESET_SMB4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NPCM7XX_RESET_SMB5 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NPCM7XX_RESET_PWM_M0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NPCM7XX_RESET_TIMER_0_4 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NPCM7XX_RESET_TIMER_5_9 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NPCM7XX_RESET_EMC2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NPCM7XX_RESET_UDC4 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NPCM7XX_RESET_UDC5 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NPCM7XX_RESET_UDC6 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NPCM7XX_RESET_UDC3 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NPCM7XX_RESET_ADC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NPCM7XX_RESET_SMB6 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NPCM7XX_RESET_SMB7 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NPCM7XX_RESET_SMB0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NPCM7XX_RESET_SMB1 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NPCM7XX_RESET_MFT0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NPCM7XX_RESET_MFT1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NPCM7XX_RESET_MFT2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NPCM7XX_RESET_MFT3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NPCM7XX_RESET_MFT4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NPCM7XX_RESET_MFT5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NPCM7XX_RESET_MFT6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NPCM7XX_RESET_MFT7 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NPCM7XX_RESET_MMC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define NPCM7XX_RESET_SDHC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define NPCM7XX_RESET_GFX_SYS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NPCM7XX_RESET_AHB_PCIBRG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NPCM7XX_RESET_VDMA 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NPCM7XX_RESET_ECE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NPCM7XX_RESET_VCD 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NPCM7XX_RESET_OTP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define NPCM7XX_RESET_SIOX1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NPCM7XX_RESET_SIOX2 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NPCM7XX_RESET_3DES 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define NPCM7XX_RESET_PSPI1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define NPCM7XX_RESET_PSPI2 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define NPCM7XX_RESET_GMAC2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define NPCM7XX_RESET_USB_HOST 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define NPCM7XX_RESET_GMAC1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define NPCM7XX_RESET_CP 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define NPCM7XX_RESET_PWM_M1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NPCM7XX_RESET_SMB12 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NPCM7XX_RESET_SPIX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NPCM7XX_RESET_SMB13 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NPCM7XX_RESET_UDC0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NPCM7XX_RESET_UDC7 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NPCM7XX_RESET_UDC8 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NPCM7XX_RESET_UDC9 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NPCM7XX_RESET_PCI_MAILBOX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NPCM7XX_RESET_SMB14 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NPCM7XX_RESET_SHA 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NPCM7XX_RESET_SEC_ECC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NPCM7XX_RESET_PCIE_RC 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NPCM7XX_RESET_TIMER_10_14 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NPCM7XX_RESET_RNG 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NPCM7XX_RESET_SMB15 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NPCM7XX_RESET_SMB8 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NPCM7XX_RESET_SMB9 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define NPCM7XX_RESET_SMB10 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define NPCM7XX_RESET_SMB11 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define NPCM7XX_RESET_ESPI 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define NPCM7XX_RESET_USB_PHY_1 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NPCM7XX_RESET_USB_PHY_2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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