Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Flora Fu, MediaTek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_RESET_CONTROLLER_MT8173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* INFRACFG resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT8173_INFRA_EMI_REG_RST        0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT8173_INFRA_DRAMC0_A0_RST      1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT8173_INFRA_APCIRQ_EINT_RST    3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MT8173_INFRA_APXGPT_RST         4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT8173_INFRA_SCPSYS_RST         5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT8173_INFRA_KP_RST             6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT8173_INFRA_PMIC_WRAP_RST      7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT8173_INFRA_MPIP_RST           8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT8173_INFRA_CEC_RST            9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT8173_INFRA_EMI_RST            32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT8173_INFRA_DRAMC0_RST         34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT8173_INFRA_APMIXEDSYS_RST     35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT8173_INFRA_MIPI_DSI_RST       36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT8173_INFRA_TRNG_RST           37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT8173_INFRA_SYSIRQ_RST         38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT8173_INFRA_MIPI_CSI_RST       39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT8173_INFRA_GCE_FAXI_RST       40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT8173_INFRA_MMIOMMURST         47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*  PERICFG resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT8173_PERI_UART0_SW_RST        0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT8173_PERI_UART1_SW_RST        1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT8173_PERI_UART2_SW_RST        2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT8173_PERI_UART3_SW_RST        3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT8173_PERI_IRRX_SW_RST         4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT8173_PERI_PWM_SW_RST          8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT8173_PERI_AUXADC_SW_RST       10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT8173_PERI_DMA_SW_RST          11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT8173_PERI_I2C6_SW_RST         13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT8173_PERI_NFI_SW_RST          14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT8173_PERI_THERM_SW_RST        16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT8173_PERI_MSDC2_SW_RST        17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT8173_PERI_MSDC3_SW_RST        18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT8173_PERI_MSDC0_SW_RST        19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT8173_PERI_MSDC1_SW_RST        20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT8173_PERI_I2C0_SW_RST         22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT8173_PERI_I2C1_SW_RST         23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT8173_PERI_I2C2_SW_RST         24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT8173_PERI_I2C3_SW_RST         25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT8173_PERI_I2C4_SW_RST         26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT8173_PERI_HDMI_SW_RST         29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT8173_PERI_SPI0_SW_RST         33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */