Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_RESET_CONTROLLER_MT7629
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* INFRACFG resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MT7629_INFRA_EMI_MPU_RST		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT7629_INFRA_UART5_RST			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT7629_INFRA_CIRQ_EINT_RST		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT7629_INFRA_APXGPT_RST			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MT7629_INFRA_SCPSYS_RST			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT7629_INFRA_KP_RST			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT7629_INFRA_SPI1_RST			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT7629_INFRA_SPI4_RST			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT7629_INFRA_SYSTIMER_RST		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT7629_INFRA_IRRX_RST			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT7629_INFRA_AO_BUS_RST			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT7629_INFRA_EMI_RST			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT7629_INFRA_APMIXED_RST		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT7629_INFRA_MIPI_RST			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT7629_INFRA_TRNG_RST			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT7629_INFRA_SYSCIRQ_RST		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT7629_INFRA_MIPI_CSI_RST		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT7629_INFRA_GCE_FAXI_RST		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT7629_INFRA_I2C_SRAM_RST		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT7629_INFRA_IOMMU_RST			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PERICFG resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT7629_PERI_UART0_SW_RST		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT7629_PERI_UART1_SW_RST		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT7629_PERI_UART2_SW_RST		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT7629_PERI_BTIF_SW_RST			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT7629_PERI_PWN_SW_RST			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT7629_PERI_DMA_SW_RST			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT7629_PERI_NFI_SW_RST			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT7629_PERI_I2C0_SW_RST			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT7629_PERI_SPI0_SW_RST			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT7629_PERI_SPI1_SW_RST			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT7629_PERI_FLASHIF_SW_RST		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PCIe Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT7629_PCIE1_CORE_RST			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT7629_PCIE1_MMIO_RST			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT7629_PCIE1_HRST			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT7629_PCIE1_USER_RST			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT7629_PCIE1_PIPE_RST			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT7629_PCIE0_CORE_RST			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT7629_PCIE0_MMIO_RST			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT7629_PCIE0_HRST			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT7629_PCIE0_USER_RST			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MT7629_PCIE0_PIPE_RST			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* SSUSB Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT7629_SSUSB_PHY_PWR_RST		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MT7629_SSUSB_MAC_PWR_RST		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* ETH Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT7629_ETHSYS_SYS_RST			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT7629_ETHSYS_MCM_RST			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT7629_ETHSYS_HSDMA_RST			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MT7629_ETHSYS_FE_RST			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MT7629_ETHSYS_ESW_RST			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MT7629_ETHSYS_GMAC_RST			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT7629_ETHSYS_EPHY_RST			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MT7629_ETHSYS_CRYPTO_RST		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MT7629_ETHSYS_PPE_RST			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */