^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_RESET_CONTROLLER_MT7622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* INFRACFG resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT7622_INFRA_EMI_REG_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT7622_INFRA_DRAMC0_A0_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT7622_INFRA_APCIRQ_EINT_RST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MT7622_INFRA_APXGPT_RST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT7622_INFRA_SCPSYS_RST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT7622_INFRA_PMIC_WRAP_RST 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT7622_INFRA_IRRX_RST 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT7622_INFRA_EMI_RST 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT7622_INFRA_WED0_RST 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT7622_INFRA_DRAMC_RST 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT7622_INFRA_CCI_INTF_RST 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT7622_INFRA_TRNG_RST 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT7622_INFRA_SYSIRQ_RST 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT7622_INFRA_WED1_RST 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* PERICFG Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT7622_PERI_UART0_SW_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT7622_PERI_UART1_SW_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT7622_PERI_UART2_SW_RST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT7622_PERI_UART3_SW_RST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT7622_PERI_UART4_SW_RST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT7622_PERI_BTIF_SW_RST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT7622_PERI_PWM_SW_RST 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT7622_PERI_AUXADC_SW_RST 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT7622_PERI_DMA_SW_RST 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT7622_PERI_IRTX_SW_RST 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT7622_PERI_NFI_SW_RST 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT7622_PERI_THERM_SW_RST 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT7622_PERI_MSDC0_SW_RST 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT7622_PERI_MSDC1_SW_RST 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT7622_PERI_I2C0_SW_RST 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT7622_PERI_I2C1_SW_RST 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT7622_PERI_I2C2_SW_RST 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT7622_PERI_SPI0_SW_RST 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT7622_PERI_SPI1_SW_RST 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT7622_PERI_FLASHIF_SW_RST 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* TOPRGU resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT7622_TOPRGU_INFRA_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT7622_TOPRGU_ETHDMA_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT7622_TOPRGU_DDRPHY_RST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT7622_TOPRGU_INFRA_AO_RST 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT7622_TOPRGU_CONN_RST 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MT7622_TOPRGU_APMIXED_RST 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT7622_TOPRGU_CONN_MCU_RST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* PCIe/SATA Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MT7622_SATA_PHY_REG_RST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MT7622_SATA_PHY_SW_RST 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MT7622_SATA_AXI_BUS_RST 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT7622_PCIE1_CORE_RST 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT7622_PCIE1_MMIO_RST 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT7622_PCIE1_HRST 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MT7622_PCIE1_USER_RST 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MT7622_PCIE1_PIPE_RST 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MT7622_PCIE0_CORE_RST 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT7622_PCIE0_MMIO_RST 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MT7622_PCIE0_HRST 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MT7622_PCIE0_USER_RST 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MT7622_PCIE0_PIPE_RST 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* SSUSB Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MT7622_SSUSB_PHY_PWR_RST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MT7622_SSUSB_MAC_PWR_RST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* ETHSYS Subsystem resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MT7622_ETHSYS_SYS_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MT7622_ETHSYS_MCM_RST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MT7622_ETHSYS_HSDMA_RST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MT7622_ETHSYS_FE_RST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MT7622_ETHSYS_GMAC_RST 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MT7622_ETHSYS_EPHY_RST 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MT7622_ETHSYS_CRYPTO_RST 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MT7622_ETHSYS_PPE_RST 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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