^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Zodiac Inflight Innovations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef DT_BINDING_RESET_IMX8MQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DT_BINDING_RESET_IMX8MQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX8MQ_RESET_A53_CORE_RESET0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8MQ_RESET_A53_CORE_RESET1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX8MQ_RESET_A53_CORE_RESET2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX8MQ_RESET_A53_CORE_RESET3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8MQ_RESET_A53_DBG_RESET0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8MQ_RESET_A53_DBG_RESET1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX8MQ_RESET_A53_DBG_RESET2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX8MQ_RESET_A53_DBG_RESET3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8MQ_RESET_A53_ETM_RESET0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8MQ_RESET_A53_ETM_RESET1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8MQ_RESET_A53_ETM_RESET2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX8MQ_RESET_A53_ETM_RESET3 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8MQ_RESET_A53_L2RESET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX8MQ_RESET_OTG1_PHY_RESET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX8MQ_RESET_DISP_RESET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8MQ_RESET_GPU_RESET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX8MQ_RESET_SW_M4C_RST 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX8MQ_RESET_SW_M4P_RST 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX8MQ_RESET_M4_ENABLE 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX8MQ_RESET_NUM 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags