Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef DT_BINDING_RESET_IMX8MP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define DT_BINDING_RESET_IMX8MP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define IMX8MP_RESET_A53_CORE_POR_RESET0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IMX8MP_RESET_A53_CORE_POR_RESET1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX8MP_RESET_A53_CORE_POR_RESET2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX8MP_RESET_A53_CORE_POR_RESET3	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8MP_RESET_A53_CORE_RESET0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8MP_RESET_A53_CORE_RESET1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX8MP_RESET_A53_CORE_RESET2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8MP_RESET_A53_CORE_RESET3		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX8MP_RESET_A53_DBG_RESET0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX8MP_RESET_A53_DBG_RESET1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8MP_RESET_A53_DBG_RESET2		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8MP_RESET_A53_DBG_RESET3		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX8MP_RESET_A53_ETM_RESET0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX8MP_RESET_A53_ETM_RESET1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8MP_RESET_A53_ETM_RESET2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8MP_RESET_A53_ETM_RESET3		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8MP_RESET_A53_SOC_DBG_RESET		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX8MP_RESET_A53_L2RESET		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8MP_RESET_SW_NON_SCLR_M7C_RST	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8MP_RESET_OTG1_PHY_RESET		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8MP_RESET_OTG2_PHY_RESET		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX8MP_RESET_SUPERMIX_RESET		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8MP_RESET_AUDIOMIX_RESET		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8MP_RESET_MLMIX_RESET		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX8MP_RESET_PCIEPHY			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8MP_RESET_PCIEPHY_PERST		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX8MP_RESET_PCIE_CTRL_APPS_EN		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8MP_RESET_HDMI_PHY_APB_RESET		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8MP_RESET_MEDIA_RESET		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX8MP_RESET_GPU2D_RESET		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8MP_RESET_GPU3D_RESET		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8MP_RESET_GPU_RESET			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX8MP_RESET_VPU_RESET			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8MP_RESET_VPU_G1_RESET		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8MP_RESET_VPU_G2_RESET		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8MP_RESET_VPUVC8KE_RESET		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8MP_RESET_NOC_RESET			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX8MP_RESET_NUM			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif