Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2017 Impinj, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef DT_BINDING_RESET_IMX7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DT_BINDING_RESET_IMX7_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX7_RESET_A7_CORE_POR_RESET0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX7_RESET_A7_CORE_POR_RESET1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX7_RESET_A7_CORE_RESET0	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX7_RESET_A7_CORE_RESET1	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX7_RESET_A7_DBG_RESET0	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX7_RESET_A7_DBG_RESET1	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX7_RESET_A7_ETM_RESET0	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX7_RESET_A7_ETM_RESET1	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX7_RESET_A7_SOC_DBG_RESET	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX7_RESET_A7_L2RESET		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX7_RESET_SW_M4C_RST		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX7_RESET_SW_M4P_RST		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX7_RESET_EIM_RST		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX7_RESET_HSICPHY_PORT_RST	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX7_RESET_USBPHY1_POR		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX7_RESET_USBPHY1_PORT_RST	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX7_RESET_USBPHY2_POR		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX7_RESET_USBPHY2_PORT_RST	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX7_RESET_MIPI_PHY_MRST	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX7_RESET_MIPI_PHY_SRST	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * and PCIEPHY_G_RST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX7_RESET_PCIEPHY		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX7_RESET_PCIEPHY_PERST	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * of as one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX7_RESET_PCIE_CTRL_APPS_EN	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX7_RESET_DDRC_PRST		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX7_RESET_DDRC_CORE_RST	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX7_RESET_NUM			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)