Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides index for the reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * based on hi6220 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_RESET_CONTROLLER_HI6220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define PERIPH_RSTDIS0_MMC0             0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PERIPH_RSTDIS0_MMC1             0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PERIPH_RSTDIS0_MMC2             0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PERIPH_RSTDIS0_NANDC            0x003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PERIPH_RSTDIS0_USBOTG_BUS       0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PERIPH_RSTDIS0_POR_PICOPHY      0x005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PERIPH_RSTDIS0_USBOTG           0x006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PERIPH_RSTDIS0_USBOTG_32K       0x007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PERIPH_RSTDIS1_HIFI             0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PERIPH_RSTDIS1_DIGACODEC        0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PERIPH_RSTEN2_IPF               0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PERIPH_RSTEN2_SOCP              0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PERIPH_RSTEN2_DMAC              0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PERIPH_RSTEN2_SECENG            0x203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PERIPH_RSTEN2_ABB               0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PERIPH_RSTEN2_HPM0              0x205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PERIPH_RSTEN2_HPM1              0x206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PERIPH_RSTEN2_HPM2              0x207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PERIPH_RSTEN2_HPM3              0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PERIPH_RSTEN3_CSSYS             0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PERIPH_RSTEN3_I2C0              0x301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PERIPH_RSTEN3_I2C1              0x302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PERIPH_RSTEN3_I2C2              0x303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PERIPH_RSTEN3_I2C3              0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PERIPH_RSTEN3_UART1             0x305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PERIPH_RSTEN3_UART2             0x306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PERIPH_RSTEN3_UART3             0x307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PERIPH_RSTEN3_UART4             0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PERIPH_RSTEN3_SSP               0x309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PERIPH_RSTEN3_PWM               0x30a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PERIPH_RSTEN3_BLPWM             0x30b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PERIPH_RSTEN3_TSENSOR           0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PERIPH_RSTEN3_DAPB              0x312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PERIPH_RSTEN3_HKADC             0x313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PERIPH_RSTEN3_CODEC_SSI         0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PERIPH_RSTEN3_PMUSSI1           0x316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PERIPH_RSTEN8_RS0               0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PERIPH_RSTEN8_RS2               0x401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PERIPH_RSTEN8_RS3               0x402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PERIPH_RSTEN8_MS0               0x403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PERIPH_RSTEN8_MS2               0x405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PERIPH_RSTEN8_XG2RAM0           0x406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PERIPH_RSTEN8_X2SRAM_TZMA       0x407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PERIPH_RSTEN8_SRAM              0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PERIPH_RSTEN8_HARQ              0x40a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PERIPH_RSTEN8_DDRC              0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PERIPH_RSTEN8_DDRC_APB          0x40d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PERIPH_RSTEN8_DDRPACK_APB       0x40e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PERIPH_RSTEN8_DDRT              0x411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PERIPH_RSDIST9_CARM_DAP         0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PERIPH_RSDIST9_CARM_ATB         0x501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PERIPH_RSDIST9_CARM_LBUS        0x502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PERIPH_RSDIST9_CARM_POR         0x503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PERIPH_RSDIST9_CARM_CORE        0x504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PERIPH_RSDIST9_CARM_DBG         0x505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PERIPH_RSDIST9_CARM_L2          0x506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PERIPH_RSDIST9_CARM_SOCDBG      0x507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PERIPH_RSDIST9_CARM_ETM         0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MEDIA_G3D                       0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MEDIA_CODEC_VPU                 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MEDIA_CODEC_JPEG                3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MEDIA_ISP                       4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MEDIA_ADE                       5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MEDIA_MMU                       6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MEDIA_XG2RAM1                   7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AO_G3D                          1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AO_CODECISP                     2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AO_MCPU                         4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AO_BBPHARQMEM                   5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AO_HIFI                         8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AO_ACPUSCUL2C                   12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/