Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 Bitmain Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (c) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_BM1880_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_BM1880_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BM1880_RST_MAIN_AP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BM1880_RST_SECOND_AP		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BM1880_RST_DDR			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BM1880_RST_VIDEO		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BM1880_RST_JPEG			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BM1880_RST_VPP			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BM1880_RST_GDMA			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BM1880_RST_AXI_SRAM		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BM1880_RST_TPU			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BM1880_RST_USB			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BM1880_RST_ETH0			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BM1880_RST_ETH1			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BM1880_RST_NAND			12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BM1880_RST_EMMC			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BM1880_RST_SD			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BM1880_RST_SDMA			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BM1880_RST_I2S0			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BM1880_RST_I2S1			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BM1880_RST_UART0_1_CLK		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BM1880_RST_UART0_1_ACLK		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BM1880_RST_UART2_3_CLK		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BM1880_RST_UART2_3_ACLK		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BM1880_RST_MINER		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BM1880_RST_I2C0			23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BM1880_RST_I2C1			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BM1880_RST_I2C2			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BM1880_RST_I2C3			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BM1880_RST_I2C4			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BM1880_RST_PWM0			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BM1880_RST_PWM1			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BM1880_RST_PWM2			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BM1880_RST_PWM3			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BM1880_RST_SPI			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM1880_RST_GPIO0		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM1880_RST_GPIO1		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BM1880_RST_GPIO2		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM1880_RST_EFUSE		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BM1880_RST_WDT			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BM1880_RST_AHB_ROM		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BM1880_RST_SPIC			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* _DT_BINDINGS_BM1880_RESET_H */