^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2018 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Qiufang Dai <qiufang.dai@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_AO_REMOTE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_AO_I2C_MASTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_AO_I2C_SLAVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_AO_UART1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_AO_UART2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_AO_IR_BLASTER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif