^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* RESET0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RESET_HIU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RESET_VLD 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RESET_IQIDCT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_MC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_VIU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_AIU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_MCPU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_CCPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_PMUX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_VENC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_ASSIST 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_AFIFO2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESET_MDEC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RESET_VLD_PART 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_VIFIFO 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 16-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* RESET1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_DEMUX 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_USB_OTG 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_DDR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_VDAC_1 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_BT656 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_AHB_SRAM 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_AHB_BRIDGE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_PARSER 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RESET_BLKMV 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_ISA 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RESET_ETHERNET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_ABUF 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RESET_AHB_DATA 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RESET_AHB_CNTL 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RESET_ROM_BOOT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 48-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* RESET2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RESET_VD_RMEM 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RESET_AUDIN 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RESET_DBLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RESET_PIC_DC 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RESET_PSC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RESET_NAND 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RESET_GE2D 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RESET_PARSER_REG 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RESET_PARSER_FETCH 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RESET_PARSER_CTL 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET_PARSER_TOP 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RESET_HDMI_APB 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RESET_AUDIO_APB 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESET_MEDIA_CPU 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RESET_MALI 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESET_HDMI_SYSTEM_RESET 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 80-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* RESET3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RESET_RING_OSCILLATOR 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RESET_SYS_CPU_0 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RESET_EFUSE 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RESET_SYS_CPU_BVCI 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RESET_AIFIFO 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RESET_AUDIO_PLL_MODULATOR 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RESET_AHB_BRIDGE_CNTL 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RESET_SYS_CPU_1 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RESET_AUDIO_DAC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RESET_DEMUX_TOP 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RESET_DEMUX_DES 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RESET_DEMUX_S2P_0 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RESET_DEMUX_S2P_1 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RESET_DEMUX_RESET_0 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RESET_DEMUX_RESET_1 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RESET_DEMUX_RESET_2 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 112-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* RESET4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RESET_PL310 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RESET_A5_APB 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RESET_A5_AXI 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RESET_A5 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RESET_DVIN 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RESET_RDMA 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RESET_VENCI 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RESET_VENCP 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RESET_VENCT 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RESET_VDAC_4 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RESET_RTC 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RESET_A5_DEBUG 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RESET_VDI6 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RESET_VENCL 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* 142-159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* RESET5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RESET_DDR_PLL 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RESET_MISC_PLL 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RESET_SYS_PLL 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RESET_HPLL_PLL 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RESET_AUDIO_PLL 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RESET_VID2_PLL 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* 166-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* RESET6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RESET_PERIPHS_GENERAL 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RESET_PERIPHS_IR_REMOTE 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RESET_PERIPHS_SMART_CARD 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RESET_PERIPHS_SAR_ADC 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RESET_PERIPHS_I2C_MASTER_0 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RESET_PERIPHS_I2C_MASTER_1 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RESET_PERIPHS_I2C_SLAVE 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RESET_PERIPHS_STREAM_INTERFACE 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RESET_PERIPHS_SDIO 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RESET_PERIPHS_UART_0 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RESET_PERIPHS_UART_1 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RESET_PERIPHS_ASYNC_0 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RESET_PERIPHS_ASYNC_1 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RESET_PERIPHS_SPI_0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RESET_PERIPHS_SPI_1 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RESET_PERIPHS_LED_PWM 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* 208-223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* RESET7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* 224-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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