^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLKC_RESET_L2_CACHE_SOFT_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLKC_RESET_SCU_SOFT_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLKC_RESET_CPU0_SOFT_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLKC_RESET_CPU1_SOFT_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLKC_RESET_CPU2_SOFT_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLKC_RESET_CPU3_SOFT_RESET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLKC_RESET_A5_GLOBAL_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLKC_RESET_A5_AXI_SOFT_RESET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLKC_RESET_A5_ABP_SOFT_RESET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */