^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* RESET0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RESET_HIU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RESET_DOS_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_DDR_TOP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_DCU_RESET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_VIU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_AIU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_VID_PLL_DIV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_PMUX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_VENC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_ASSIST 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_AFIFO2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESET_VCBUS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_GIC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_CAPB3_DECODE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_NAND_CAPB3 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_HDMITX_CAPB3 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_MALI_CAPB3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_DOS_CAPB3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_SYS_CPU_CAPB3 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_CBUS_CAPB3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_AHB_CNTL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_AHB_DATA 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_VCBUS_CLK81 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RESET_MMC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_MIPI_0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RESET_MIPI_1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_MIPI_2 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RESET_MIPI_3 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* RESET1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RESET_CPPM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RESET_DEMUX 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RESET_USB_OTG 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RESET_DDR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RESET_AO_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RESET_BT656 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RESET_AHB_SRAM 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RESET_PARSER 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RESET_BLKMV 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RESET_ISA 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RESET_ETHERNET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RESET_SD_EMMC_A 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET_SD_EMMC_B 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RESET_SD_EMMC_C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RESET_ROM_BOOT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESET_SYS_CPU_0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RESET_SYS_CPU_1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESET_SYS_CPU_2 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RESET_SYS_CPU_3 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RESET_SYS_CPU_CORE_0 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RESET_SYS_CPU_CORE_1 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RESET_SYS_CPU_CORE_2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RESET_SYS_CPU_CORE_3 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RESET_SYS_PLL_DIV 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RESET_SYS_CPU_AXI 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RESET_SYS_CPU_L2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RESET_SYS_CPU_P 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RESET_SYS_CPU_MBIST 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RESET_ACODEC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* 62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* RESET2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RESET_VD_RMEM 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RESET_AUDIN 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RESET_HDMI_TX 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* 69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RESET_GE2D 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RESET_PARSER_REG 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RESET_PARSER_FETCH 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RESET_PARSER_CTL 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RESET_PARSER_TOP 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* 76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RESET_AO_CPU_RESET 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RESET_MALI 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RESET_HDMI_SYSTEM_RESET 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* 80-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* RESET3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RESET_RING_OSCILLATOR 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RESET_SYS_CPU 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RESET_EFUSE 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RESET_SYS_CPU_BVCI 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RESET_AIFIFO 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RESET_TVFE 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RESET_AHB_BRIDGE_CNTL 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* 103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RESET_AUDIO_DAC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RESET_DEMUX_TOP 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RESET_DEMUX_DES 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RESET_DEMUX_S2P_0 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RESET_DEMUX_S2P_1 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RESET_DEMUX_RESET_0 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RESET_DEMUX_RESET_1 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RESET_DEMUX_RESET_2 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* 112-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* RESET4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* 130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RESET_DVIN_RESET 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RESET_RDMA 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RESET_VENCI 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RESET_VENCP 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 136 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RESET_VDAC 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RESET_RTC 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* 139 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RESET_VDI6 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RESET_VENCL 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RESET_I2C_MASTER_2 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RESET_I2C_MASTER_1 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 144-159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* RESET5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* 160-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* RESET6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RESET_PERIPHS_GENERAL 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RESET_PERIPHS_SPICC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RESET_PERIPHS_SMART_CARD 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RESET_PERIPHS_SAR_ADC 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RESET_PERIPHS_I2C_MASTER_0 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RESET_SANA 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* 198 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RESET_PERIPHS_STREAM_INTERFACE 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RESET_PERIPHS_SDIO 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RESET_PERIPHS_UART_0 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RESET_PERIPHS_UART_1_2 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RESET_PERIPHS_ASYNC_0 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RESET_PERIPHS_ASYNC_1 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RESET_PERIPHS_SPI_0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RESET_PERIPHS_SDHC 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RESET_UART_SLIP 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* 208-223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* RESET7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RESET_USB_DDR_0 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RESET_USB_DDR_1 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RESET_USB_DDR_2 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RESET_USB_DDR_3 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 228 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RESET_DEVICE_MMC_ARB 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RESET_VID_LOCK 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RESET_A9_DMC_PIPEL 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* 233-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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