^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jerome Brunet <jbrunet@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* RESET0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RESET_HIU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_DOS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* 3-4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_VIU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_AFIFO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_VID_PLL_DIV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* 8-9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_VENC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_ASSIST 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_PCIE_CTRL_A 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESET_VCBUS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RESET_PCIE_PHY 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_PCIE_APB 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_GIC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_CAPB3_DECODE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_HDMITX_CAPB3 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_DVALIN_CAPB3 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_DOS_CAPB3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_CBUS_CAPB3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_AHB_CNTL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_AHB_DATA 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_VCBUS_CLK81 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* 27-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* RESET1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_DEMUX 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RESET_USB 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RESET_DDR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RESET_BT656 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RESET_AHB_SRAM 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RESET_PARSER 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* 41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RESET_ISA 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RESET_ETHERNET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RESET_SD_EMMC_A 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RESET_SD_EMMC_B 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RESET_SD_EMMC_C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* 47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RESET_USB_PHY20 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET_USB_PHY21 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* 50-60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RESET_AUDIO_CODEC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* 62-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* RESET2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RESET_AUDIO 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RESET_HDMITX_PHY 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* 67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RESET_MIPI_DSI_HOST 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RESET_ALOCKER 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RESET_GE2D 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RESET_PARSER_REG 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RESET_PARSER_FETCH 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RESET_CTL 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RESET_PARSER_TOP 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* 75-77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RESET_DVALIN 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RESET_HDMITX 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* 80-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* RESET3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 96-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RESET_DEMUX_TOP 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RESET_DEMUX_DES_PL 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RESET_DEMUX_S2P_0 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RESET_DEMUX_S2P_1 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RESET_DEMUX_0 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RESET_DEMUX_1 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RESET_DEMUX_2 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 112-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* RESET4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 128-129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RESET_MIPI_DSI_PHY 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* 131-132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RESET_RDMA 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RESET_VENCI 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RESET_VENCP 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* 136 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RESET_VDAC 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* 138-139 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RESET_VDI6 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RESET_VENCL 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RESET_I2C_M1 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RESET_I2C_M2 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* 144-159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* RESET5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 160-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* RESET6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RESET_GEN 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RESET_SPICC0 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RESET_SC 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RESET_SANA_3 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RESET_I2C_M0 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RESET_TS_PLL 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RESET_SPICC1 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RESET_STREAM 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RESET_TS_CPU 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RESET_UART0 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RESET_UART1_2 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RESET_ASYNC0 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RESET_ASYNC1 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RESET_SPIFC0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RESET_I2C_M3 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 207-223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* RESET7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RESET_USB_DDR_0 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RESET_USB_DDR_1 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RESET_USB_DDR_2 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RESET_USB_DDR_3 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RESET_TS_GPU 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RESET_DEVICE_MMC_ARB 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RESET_DVALIN_DMC_PIPL 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RESET_VID_LOCK 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RESET_NIC_DMC_PIPL 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RESET_DMC_VPU_PIPL 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RESET_GE2D_DMC_PIPL 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RESET_HCODEC_DMC_PIPL 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RESET_WAVE420_DMC_PIPL 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RESET_HEVCF_DMC_PIPL 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 238-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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