^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016 BayLibre, SAS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2017 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Yixun Lan <yixun.lan@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* RESET0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_HIU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_PCIE_A 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_PCIE_B 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_DDR_TOP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_VIU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_PCIE_PHY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_PCIE_APB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_VENC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_ASSIST 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_VCBUS 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_GIC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_CAPB3_DECODE 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* 18-21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_SYS_CPU_CAPB3 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_CBUS_CAPB3 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_AHB_CNTL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RESET_AHB_DATA 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_VCBUS_CLK81 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RESET_MMC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* 28-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* RESET1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RESET_USB_OTG 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RESET_DDR 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RESET_AO_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RESET_AHB_SRAM 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RESET_DMA 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RESET_ISA 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RESET_ETHERNET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* 44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RESET_SD_EMMC_B 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET_SD_EMMC_C 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RESET_ROM_BOOT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RESET_SYS_CPU_0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESET_SYS_CPU_1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RESET_SYS_CPU_2 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESET_SYS_CPU_3 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RESET_SYS_CPU_CORE_0 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RESET_SYS_CPU_CORE_1 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RESET_SYS_CPU_CORE_2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RESET_SYS_CPU_CORE_3 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RESET_SYS_PLL_DIV 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RESET_SYS_CPU_AXI 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RESET_SYS_CPU_L2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RESET_SYS_CPU_P 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RESET_SYS_CPU_MBIST 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* 61-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* RESET2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* 65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RESET_AUDIO 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* 67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RESET_MIPI_HOST 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RESET_AUDIO_LOCKER 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RESET_GE2D 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 71-76 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RESET_AO_CPU_RESET 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* 78-95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* RESET3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RESET_RING_OSCILLATOR 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* 97-127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* RESET4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* 129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RESET_MIPI_PHY 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 131-140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RESET_VENCL 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RESET_I2C_MASTER_2 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RESET_I2C_MASTER_1 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* 144-159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* RESET5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* 160-191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* RESET6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RESET_PERIPHS_GENERAL 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RESET_PERIPHS_SPICC 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* 194 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* 195 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RESET_PERIPHS_I2C_MASTER_0 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* 197-200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RESET_PERIPHS_UART_0 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RESET_PERIPHS_UART_1 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* 203-204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RESET_PERIPHS_SPI_0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RESET_PERIPHS_I2C_MASTER_3 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 207-223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* RESET7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RESET_USB_DDR_0 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RESET_USB_DDR_1 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RESET_USB_DDR_2 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RESET_USB_DDR_3 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 228 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RESET_DEVICE_MMC_ARB 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RESET_VID_LOCK 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RESET_A9_DMC_PIPEL 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RESET_DMC_VPU_PIPEL 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* 234-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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