Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* MPUMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CPU0_RESET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CPU1_RESET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define WDS_RESET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SCUPER_RESET		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define L2_RESET		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PERMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EMAC0_RESET		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EMAC1_RESET		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define USB0_RESET		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USB1_RESET		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NAND_RESET		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QSPI_RESET		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define L4WD0_RESET		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define L4WD1_RESET		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OSC1TIMER0_RESET	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OSC1TIMER1_RESET	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPTIMER0_RESET		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPTIMER1_RESET		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define I2C0_RESET		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define I2C1_RESET		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define I2C2_RESET		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define I2C3_RESET		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define UART0_RESET		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UART1_RESET		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPIM0_RESET		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPIM1_RESET		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPIS0_RESET		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPIS1_RESET		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SDMMC_RESET		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CAN0_RESET		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CAN1_RESET		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO0_RESET		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO1_RESET		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO2_RESET		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMA_RESET		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SDR_RESET		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* PER2MODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMAIF0_RESET		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMAIF1_RESET		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DMAIF2_RESET		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DMAIF3_RESET		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DMAIF4_RESET		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DMAIF5_RESET		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMAIF6_RESET		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMAIF7_RESET		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* BRGMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HPS2FPGA_RESET		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LWHPS2FPGA_RESET	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FPGA2HPS_RESET		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* MISCMODRST*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ROM_RESET		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OCRAM_RESET		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SYSMGR_RESET		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SYSMGRCOLD_RESET	131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FPGAMGR_RESET		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ACPIDMAP_RESET		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S2F_RESET		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S2FCOLD_RESET		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NRSTPIN_RESET		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TIMESTAMPCOLD_RESET	137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLKMGRCOLD_RESET	138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SCANMGR_RESET		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FRZCTRLCOLD_RESET	140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SYSDBG_RESET		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DBG_RESET		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TAPCOLD_RESET		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SDRCOLD_RESET		144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif