Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Intel Corporation. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2016 Altera Corporation. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* MPUMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPU0_RESET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU1_RESET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CPU2_RESET		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPU3_RESET		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* PER0MODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EMAC0_RESET		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EMAC1_RESET		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EMAC2_RESET		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USB0_RESET		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define USB1_RESET		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NAND_RESET		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* 38 is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SDMMC_RESET		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EMAC0_OCP_RESET		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EMAC1_OCP_RESET		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EMAC2_OCP_RESET		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define USB0_OCP_RESET		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define USB1_OCP_RESET		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NAND_OCP_RESET		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* 46 is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SDMMC_OCP_RESET		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMA_RESET		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPIM0_RESET		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPIM1_RESET		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPIS0_RESET		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPIS1_RESET		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_OCP_RESET		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EMAC_PTP_RESET		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* 55 is empty*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMAIF0_RESET		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMAIF1_RESET		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMAIF2_RESET		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DMAIF3_RESET		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMAIF4_RESET		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DMAIF5_RESET		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMAIF6_RESET		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMAIF7_RESET		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PER1MODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WATCHDOG0_RESET		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WATCHDOG1_RESET		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WATCHDOG2_RESET		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WATCHDOG3_RESET		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define L4SYSTIMER0_RESET	68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define L4SYSTIMER1_RESET	69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPTIMER0_RESET		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPTIMER1_RESET		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C0_RESET		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C1_RESET		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C2_RESET		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C3_RESET		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C4_RESET		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* 77-79 is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UART0_RESET		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UART1_RESET		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* 82-87 is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPIO0_RESET		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO1_RESET		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* BRGMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SOC2FPGA_RESET		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LWHPS2FPGA_RESET	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FPGA2SOC_RESET		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define F2SSDRAM0_RESET		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define F2SSDRAM1_RESET		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define F2SSDRAM2_RESET		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DDRSCH_RESET		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* COLDMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CPUPO0_RESET		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CPUPO1_RESET		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CPUPO2_RESET		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CPUPO3_RESET		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* 164-167 is empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define L2_RESET		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* DBGMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DBG_RESET		224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CSDAP_RESET		225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* TAPMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TAP_RESET		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif