Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Copyright Intel Corporation (C) 2017. All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Adapted from altr,rst-mgr-a10.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Peripheral PHY resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define A10SR_RESET_ENET_HPS	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define A10SR_RESET_PCIE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define A10SR_RESET_FILE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define A10SR_RESET_BQSPI	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define A10SR_RESET_USB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define A10SR_RESET_NUM		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif