^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* MPUMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CPU0_RESET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CPU1_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define WDS_RESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SCUPER_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* PER0MODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EMAC0_RESET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EMAC1_RESET 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EMAC2_RESET 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define USB0_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USB1_RESET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NAND_RESET 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QSPI_RESET 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SDMMC_RESET 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EMAC0_OCP_RESET 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMAC1_OCP_RESET 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EMAC2_OCP_RESET 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define USB0_OCP_RESET 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define USB1_OCP_RESET 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NAND_OCP_RESET 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QSPI_OCP_RESET 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SDMMC_OCP_RESET 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DMA_RESET 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPIM0_RESET 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPIM1_RESET 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPIS0_RESET 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPIS1_RESET 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_OCP_RESET 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EMAC_PTP_RESET 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* 55 is empty*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMAIF0_RESET 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DMAIF1_RESET 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DMAIF2_RESET 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMAIF3_RESET 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMAIF4_RESET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMAIF5_RESET 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DMAIF6_RESET 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMAIF7_RESET 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* PER1MODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define L4WD0_RESET 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define L4WD1_RESET 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define L4SYSTIMER0_RESET 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define L4SYSTIMER1_RESET 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPTIMER0_RESET 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPTIMER1_RESET 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 70-71 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2C0_RESET 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2C1_RESET 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2C2_RESET 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C3_RESET 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C4_RESET 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 77-79 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UART0_RESET 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UART1_RESET 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 82-87 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPIO0_RESET 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPIO1_RESET 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPIO2_RESET 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* BRGMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HPS2FPGA_RESET 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LWHPS2FPGA_RESET 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FPGA2HPS_RESET 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define F2SSDRAM0_RESET 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define F2SSDRAM1_RESET 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define F2SSDRAM2_RESET 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DDRSCH_RESET 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SYSMODRST*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ROM_RESET 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OCRAM_RESET 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* 130 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FPGAMGR_RESET 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define S2F_RESET 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SYSDBG_RESET 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OCRAM_OCP_RESET 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* COLDMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLKMGRCOLD_RESET 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* 161-162 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S2FCOLD_RESET 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TIMESTAMPCOLD_RESET 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TAPCOLD_RESET 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HMCCOLD_RESET 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IOMGRCOLD_RESET 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* NRSTMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define NRSTPINOE_RESET 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* DBGMODRST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DBG_RESET 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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