Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Device Tree binding constants for Actions Semi S900 Reset Management Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) // Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __DT_BINDINGS_ACTIONS_S900_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RESET_CHIPID				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RESET_CPU_SCNT				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RESET_SRAMI				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_DDR_CTL_PHY			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_DMAC				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_GPIO				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_BISP_AXI				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_CSI0				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_CSI1				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_DE				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_DSI				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_GPU3D_PA				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_GPU3D_PB				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESET_HDE				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RESET_I2C0				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_I2C1				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_I2C2				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_I2C3				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_I2C4				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_I2C5				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_IMX				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_NANDC0				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_NANDC1				22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_SD0				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_SD1				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_SD2				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_SD3				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RESET_SPI0				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_SPI1				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RESET_SPI2				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_SPI3				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RESET_UART0				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RESET_UART1				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RESET_UART2				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RESET_UART3				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RESET_UART4				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RESET_UART5				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RESET_UART6				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RESET_HDMI				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RESET_LVDS				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RESET_EDP				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RESET_USB2HUB				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RESET_USB2HSIC				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RESET_USB3				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RESET_PCM1				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RESET_AUDIO				45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET_PCM0				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RESET_SE				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RESET_GIC				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESET_DDR_CTL_PHY_AXI			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RESET_CMU_DDR				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESET_DMM				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RESET_HDCP2TX				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RESET_ETHERNET				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */