Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree binding constants for Actions Semi S500 Reset Management Unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __DT_BINDINGS_ACTIONS_S500_RESET_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RESET_DMAC				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RESET_NORIF				1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RESET_DDR				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RESET_NANDC				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RESET_SD0				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RESET_SD1				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RESET_PCM1				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RESET_DE				7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RESET_LCD				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RESET_SD2				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RESET_DSI				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RESET_CSI				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RESET_BISP				12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RESET_KEY				13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RESET_GPIO				14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RESET_AUDIO				15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RESET_PCM0				16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_VDE				17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RESET_VCE				18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RESET_GPU3D				19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RESET_NIC301				20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RESET_LENS				21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RESET_PERIPHRESET			22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RESET_USB2_0				23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RESET_TVOUT				24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RESET_HDMI				25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RESET_HDCP2TX				26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RESET_UART6				27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RESET_UART0				28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RESET_UART1				29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RESET_UART2				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RESET_SPI0				31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RESET_SPI1				32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RESET_SPI2				33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RESET_SPI3				34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RESET_I2C0				35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RESET_I2C1				36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RESET_USB3				37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RESET_UART3				38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RESET_UART4				39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RESET_UART5				40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RESET_I2C2				41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RESET_I2C3				42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RESET_ETHERNET				43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RESET_CHIPID				44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RESET_USB2_1				45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RESET_WD0RESET				46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESET_WD1RESET				47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RESET_WD2RESET				48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RESET_WD3RESET				49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RESET_DBG0RESET				50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RESET_DBG1RESET				51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RESET_DBG2RESET				52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RESET_DBG3RESET				53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */