^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Yong Liang <yong.liang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_RESET_CONTROLLER_MT8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* INFRACFG AO resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT8183_INFRACFG_AO_THERM_SW_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MT8183_INFRACFG_AO_MSDC3_SW_RST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT8183_INFRACFG_AO_MSDC2_SW_RST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT8183_INFRACFG_AO_MSDC1_SW_RST 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT8183_INFRACFG_AO_MSDC0_SW_RST 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT8183_INFRACFG_AO_APDMA_SW_RST 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT8183_INFRACFG_AO_BTIF_SW_RST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT8183_INFRACFG_AO_AUXADC_SW_RST 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT8183_INFRACFG_AO_IRTX_SW_RST 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT8183_INFRACFG_AO_SPI0_SW_RST 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT8183_INFRACFG_AO_I2C0_SW_RST 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT8183_INFRACFG_AO_I2C1_SW_RST 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT8183_INFRACFG_AO_I2C2_SW_RST 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT8183_INFRACFG_AO_I2C3_SW_RST 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT8183_INFRACFG_AO_UART0_SW_RST 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT8183_INFRACFG_AO_UART1_SW_RST 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT8183_INFRACFG_AO_UART2_SW_RST 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT8183_INFRACFG_AO_PWM_SW_RST 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT8183_INFRACFG_AO_SPI1_SW_RST 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT8183_INFRACFG_AO_I2C4_SW_RST 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT8183_INFRACFG_AO_DVFSP_SW_RST 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT8183_INFRACFG_AO_SPI2_SW_RST 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT8183_INFRACFG_AO_SPI3_SW_RST 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT8183_INFRACFG_AO_SPM_SW_RST 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT8183_INFRACFG_AO_USBSIF_SW_RST 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT8183_INFRACFG_AO_KP_SW_RST 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT8183_INFRACFG_AO_APXGPT_SW_RST 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT8183_INFRACFG_AO_DX_CC_SW_RST 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT8183_INFRACFG_AO_GCE_SW_RST 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT8183_INFRACFG_AO_CLDMA_SW_RST 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MT8183_INFRACFG_AO_TRNG_SW_RST 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT8183_INFRACFG_AO_I2C5_SW_RST 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MT8183_INFRACFG_AO_SPI4_SW_RST 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MT8183_INFRACFG_AO_SPI5_SW_RST 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MT8183_INFRACFG_AO_I2C6_SW_RST 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MT8183_INFRACFG_AO_I2C7_SW_RST 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MT8183_INFRACFG_AO_I2C8_SW_RST 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MT8183_INFRACFG_SW_RST_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MT8183_TOPRGU_MM_SW_RST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MT8183_TOPRGU_MFG_SW_RST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MT8183_TOPRGU_VENC_SW_RST 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MT8183_TOPRGU_VDEC_SW_RST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MT8183_TOPRGU_IMG_SW_RST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MT8183_TOPRGU_MD_SW_RST 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MT8183_TOPRGU_CONN_SW_RST 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MT8183_TOPRGU_CONN_MCU_SW_RST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MT8183_TOPRGU_IPU0_SW_RST 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MT8183_TOPRGU_IPU1_SW_RST 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MT8183_TOPRGU_AUDIO_SW_RST 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MT8183_TOPRGU_CAMSYS_SW_RST 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MT8183_TOPRGU_SW_RST_NUM 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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