Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Yong Liang <yong.liang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_RESET_CONTROLLER_MT2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MT2712_TOPRGU_INFRA_SW_RST				0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT2712_TOPRGU_MM_SW_RST					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT2712_TOPRGU_MFG_SW_RST				2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT2712_TOPRGU_VENC_SW_RST				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MT2712_TOPRGU_VDEC_SW_RST				4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT2712_TOPRGU_IMG_SW_RST				5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT2712_TOPRGU_INFRA_AO_SW_RST				8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT2712_TOPRGU_USB_SW_RST				9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT2712_TOPRGU_APMIXED_SW_RST				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT2712_TOPRGU_SW_RST_NUM				11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */