Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  Copyright (C) 2018 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_ZYNQMP_POWER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_ZYNQMP_POWER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define		PD_USB_0	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define		PD_USB_1	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define		PD_TTC_0	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define		PD_TTC_1	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define		PD_TTC_2	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define		PD_TTC_3	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define		PD_SATA		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define		PD_ETH_0	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define		PD_ETH_1	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define		PD_ETH_2	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define		PD_ETH_3	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define		PD_UART_0	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define		PD_UART_1	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define		PD_SPI_0	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define		PD_SPI_1	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define		PD_I2C_0	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define		PD_I2C_1	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define		PD_SD_0		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define		PD_SD_1		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define		PD_DP		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define		PD_GDMA		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define		PD_ADMA		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define		PD_NAND		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define		PD_QSPI		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define		PD_GPIO		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define		PD_CAN_0	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define		PD_CAN_1	48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define		PD_GPU		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define		PD_PCIE		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif