Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifndef __ABI_MACH_T194_POWERGATE_T194_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define __ABI_MACH_T194_POWERGATE_T194_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define TEGRA194_POWER_DOMAIN_AUD	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define TEGRA194_POWER_DOMAIN_DISP	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define TEGRA194_POWER_DOMAIN_DISPB	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA194_POWER_DOMAIN_DISPC	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA194_POWER_DOMAIN_ISPA	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA194_POWER_DOMAIN_NVDECA	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA194_POWER_DOMAIN_NVJPG	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA194_POWER_DOMAIN_NVENCA	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA194_POWER_DOMAIN_NVENCB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA194_POWER_DOMAIN_NVDECB	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA194_POWER_DOMAIN_SAX	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA194_POWER_DOMAIN_VE	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA194_POWER_DOMAIN_VIC	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA194_POWER_DOMAIN_XUSBA	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA194_POWER_DOMAIN_XUSBB	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA194_POWER_DOMAIN_XUSBC	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA194_POWER_DOMAIN_PCIEX8A	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA194_POWER_DOMAIN_PCIEX4A	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA194_POWER_DOMAIN_PCIEX1A	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA194_POWER_DOMAIN_PCIEX8B	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA194_POWER_DOMAIN_PVAA	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA194_POWER_DOMAIN_PVAB	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA194_POWER_DOMAIN_DLAA	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA194_POWER_DOMAIN_DLAB	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA194_POWER_DOMAIN_CV	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA194_POWER_DOMAIN_GPU	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA194_POWER_DOMAIN_MAX	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif