Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __DT_BINDINGS_POWER_RK3588_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* VD_LITDSU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define RK3588_PD_CPU_0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define RK3588_PD_CPU_1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define RK3588_PD_CPU_2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define RK3588_PD_CPU_3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* VD_BIGCORE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RK3588_PD_CPU_4		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RK3588_PD_CPU_5		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* VD_BIGCORE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK3588_PD_CPU_6		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3588_PD_CPU_7		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* VD_NPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK3588_PD_NPU		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RK3588_PD_NPUTOP	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RK3588_PD_NPU1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RK3588_PD_NPU2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* VD_GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RK3588_PD_GPU		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* VD_VCODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RK3588_PD_VCODEC	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RK3588_PD_RKVDEC0	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RK3588_PD_RKVDEC1	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RK3588_PD_VENC0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RK3588_PD_VENC1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* VD_DD01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RK3588_PD_DDR01		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* VD_DD23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RK3588_PD_DDR23		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RK3588_PD_CENTER	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RK3588_PD_VDPU		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RK3588_PD_RGA30		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RK3588_PD_AV1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RK3588_PD_VOP		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RK3588_PD_VO0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RK3588_PD_VO1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RK3588_PD_VI		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RK3588_PD_ISP1		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RK3588_PD_FEC		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RK3588_PD_RGA31		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RK3588_PD_USB		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RK3588_PD_PHP		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RK3588_PD_GMAC		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RK3588_PD_PCIE		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RK3588_PD_NVM		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RK3588_PD_NVM0		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RK3588_PD_SDIO		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RK3588_PD_AUDIO		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RK3588_PD_SECURE	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK3588_PD_SDMMC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK3588_PD_CRYPTO	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RK3588_PD_BUS		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* VD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RK3588_PD_PMU1		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif