Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __DT_BINDINGS_POWER_RK3399_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __DT_BINDINGS_POWER_RK3399_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* VD_CORE_L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define RK3399_PD_A53_L0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define RK3399_PD_A53_L1	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define RK3399_PD_A53_L2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define RK3399_PD_A53_L3	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RK3399_PD_SCU_L		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* VD_CORE_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RK3399_PD_A72_B0	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RK3399_PD_A72_B1	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK3399_PD_SCU_B		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3399_PD_TCPD0		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3399_PD_TCPD1		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK3399_PD_CCI		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RK3399_PD_CCI0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RK3399_PD_CCI1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RK3399_PD_PERILP	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RK3399_PD_PERIHP	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RK3399_PD_VIO		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RK3399_PD_VO		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RK3399_PD_VOPB		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RK3399_PD_VOPL		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RK3399_PD_ISP0		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RK3399_PD_ISP1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RK3399_PD_HDCP		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RK3399_PD_GMAC		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RK3399_PD_EMMC		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RK3399_PD_USB3		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RK3399_PD_EDP		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RK3399_PD_GIC		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RK3399_PD_SD		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RK3399_PD_SDIOAUDIO	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RK3399_PD_ALIVE		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* VD_CENTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RK3399_PD_CENTER	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RK3399_PD_VCODEC	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RK3399_PD_VDU		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RK3399_PD_RGA		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RK3399_PD_IEP		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* VD_GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RK3399_PD_GPU		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* VD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RK3399_PD_PMU		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif