^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DT_BINDINGS_POWER_RK3368_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DT_BINDINGS_POWER_RK3368_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* VD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define RK3368_PD_A53_L0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define RK3368_PD_A53_L1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define RK3368_PD_A53_L2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RK3368_PD_A53_L3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RK3368_PD_SCU_L 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RK3368_PD_A53_B0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RK3368_PD_A53_B1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RK3368_PD_A53_B2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RK3368_PD_A53_B3 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK3368_PD_SCU_B 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3368_PD_BUS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3368_PD_PERI 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK3368_PD_VIO 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RK3368_PD_ALIVE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RK3368_PD_VIDEO 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RK3368_PD_GPU_0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RK3368_PD_GPU_1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* VD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RK3368_PD_PMU 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif