^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DT_BINDINGS_POWER_RK3366_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DT_BINDINGS_POWER_RK3366_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* VD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define RK3366_PD_A53_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define RK3366_PD_A53_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define RK3366_PD_A53_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RK3366_PD_A53_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RK3366_PD_BUS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RK3366_PD_PERI 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RK3366_PD_VIO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK3366_PD_VIDEO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK3366_PD_RKVDEC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3366_PD_WIFIBT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3366_PD_VPU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3366_PD_GPU 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RK3366_PD_ALIVE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* VD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RK3366_PD_PMU 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif