^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DT_BINDINGS_POWER_RK3228_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * RK3228 idle id Summary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RK3228_PD_CORE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RK3228_PD_MSCH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RK3228_PD_BUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RK3228_PD_SYS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RK3228_PD_VIO 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RK3228_PD_VOP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK3228_PD_VPU 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK3228_PD_RKVDEC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3228_PD_GPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3228_PD_PERI 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3228_PD_GMAC 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif