^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DT_BINDINGS_POWER_RK3188_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* VD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define RK3188_PD_A9_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define RK3188_PD_A9_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define RK3188_PD_A9_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RK3188_PD_A9_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define RK3188_PD_DBG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RK3188_PD_SCU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RK3188_PD_VIDEO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK3188_PD_VIO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK3188_PD_GPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK3188_PD_PERI 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK3188_PD_CPU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RK3188_PD_ALIVE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* VD_PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RK3188_PD_RTC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif