^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DT_BINDINGS_POWER_RK1808_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DT_BINDINGS_POWER_RK1808_POWER_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* VD_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define RK1808_PD_A35_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define RK1808_PD_A35_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define RK1808_PD_SCU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RK1808_VD_CORE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* VD_NPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RK1808_VD_NPU 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* VD_LOGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RK1808_PD_DDR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RK1808_PD_PCIE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RK1808_PD_VPU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RK1808_PD_VIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif